| Message ID | 20200725145056.537060-1-marex@denx.de |
|---|---|
| State | Accepted |
| Commit | 8791cf09231c1ff13faa221bef138915d27ad78c |
| Delegated to: | Patrice Chotard |
| Headers | show |
| Series | [1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT | expand |
Hi Marek On 7/25/20 4:50 PM, Marek Vasut wrote: > The PHY and the VIO regulator is populated on the SoM, move it > into the SoM DT. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Patrice Chotard <patrice.chotard@st.com> > Cc: Patrick Delaunay <patrick.delaunay@st.com> > --- > arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 69 ------------------------- > arch/arm/dts/stm32mp15xx-dhcom.dtsi | 69 +++++++++++++++++++++++++ > 2 files changed, 69 insertions(+), 69 deletions(-) > > diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts > index dd98c7abee..52a77c4123 100644 > --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts > +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts > @@ -11,78 +11,9 @@ > > aliases { > serial0 = &uart4; > - ethernet0 = ðernet0; > }; > > chosen { > stdout-path = "serial0:115200n8"; > }; > - > - ethernet_vio: vioregulator { > - compatible = "regulator-fixed"; > - regulator-name = "vio"; > - regulator-min-microvolt = <3300000>; > - regulator-max-microvolt = <3300000>; > - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; > - regulator-always-on; > - regulator-boot-on; > - }; > -}; > - > -ðernet0 { > - status = "okay"; > - pinctrl-0 = <ðernet0_rmii_pins_a>; > - pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; > - pinctrl-names = "default", "sleep"; > - phy-mode = "rmii"; > - max-speed = <100>; > - phy-handle = <&phy0>; > - st,eth_ref_clk_sel; > - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; > - > - mdio0 { > - #address-cells = <1>; > - #size-cells = <0>; > - compatible = "snps,dwmac-mdio"; > - > - phy0: ethernet-phy@1 { > - reg = <1>; > - }; > - }; > -}; > - > -&pinctrl { > - ethernet0_rmii_pins_a: rmii-0 { > - pins1 { > - pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ > - <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ > - <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ > - <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ > - <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ > - <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ > - bias-disable; > - drive-push-pull; > - slew-rate = <2>; > - }; > - pins2 { > - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ > - <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ > - <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ > - bias-disable; > - }; > - }; > - > - ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { > - pins1 { > - pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ > - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ > - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ > - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ > - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ > - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ > - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ > - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ > - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ > - }; > - }; > }; > diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi > index b3f4cb4515..643aec94ce 100644 > --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi > +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi > @@ -14,12 +14,23 @@ > / { > aliases { > eeprom0 = &eeprom0; > + ethernet0 = ðernet0; > }; > > memory@c0000000 { > device_type = "memory"; > reg = <0xC0000000 0x40000000>; > }; > + > + ethernet_vio: vioregulator { > + compatible = "regulator-fixed"; > + regulator-name = "vio"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; > + regulator-always-on; > + regulator-boot-on; > + }; > }; > > &cec { > @@ -39,6 +50,28 @@ > status = "okay"; > }; > > +ðernet0 { > + status = "okay"; > + pinctrl-0 = <ðernet0_rmii_pins_a>; > + pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; > + pinctrl-names = "default", "sleep"; > + phy-mode = "rmii"; > + max-speed = <100>; > + phy-handle = <&phy0>; > + st,eth_ref_clk_sel; > + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; > + > + mdio0 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dwmac-mdio"; > + > + phy0: ethernet-phy@1 { > + reg = <1>; > + }; > + }; > +}; > + > &i2c2 { > pinctrl-names = "default"; > pinctrl-0 = <&i2c2_pins_a>; > @@ -228,6 +261,42 @@ > vdd_3v3_usbfs-supply = <&vdd_usb>; > }; > > +&pinctrl { > + ethernet0_rmii_pins_a: rmii-0 { > + pins1 { > + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ > + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ > + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ > + <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ > + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ > + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ > + bias-disable; > + drive-push-pull; > + slew-rate = <2>; > + }; > + pins2 { > + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ > + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ > + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ > + bias-disable; > + }; > + }; > + > + ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { > + pins1 { > + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ > + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ > + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ > + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ > + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ > + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ > + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ > + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ > + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ > + }; > + }; > +}; > + > &qspi { > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Thanks Patrice
Hi Marek, > From: Marek Vasut <marex@denx.de> > Sent: samedi 25 juillet 2020 16:51 > To: u-boot@lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Patrice CHOTARD > <patrice.chotard@st.com>; Patrick DELAUNAY <patrick.delaunay@st.com> > Subject: [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT > Importance: High > > The PHY and the VIO regulator is populated on the SoM, move it into the SoM DT. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Patrice Chotard <patrice.chotard@st.com> > Cc: Patrick Delaunay <patrick.delaunay@st.com> > --- > arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 69 ------------------------- > arch/arm/dts/stm32mp15xx-dhcom.dtsi | 69 +++++++++++++++++++++++++ > 2 files changed, 69 insertions(+), 69 deletions(-) > Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Thanks Patrick
On 7/28/20 11:00 AM, Patrice CHOTARD wrote: > Hi Marek > > On 7/25/20 4:50 PM, Marek Vasut wrote: >> The PHY and the VIO regulator is populated on the SoM, move it >> into the SoM DT. >> >> Signed-off-by: Marek Vasut <marex@denx.de> >> Cc: Patrice Chotard <patrice.chotard@st.com> >> Cc: Patrick Delaunay <patrick.delaunay@st.com> >> --- >> arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 69 ------------------------- >> arch/arm/dts/stm32mp15xx-dhcom.dtsi | 69 +++++++++++++++++++++++++ >> 2 files changed, 69 insertions(+), 69 deletions(-) >> >> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts >> index dd98c7abee..52a77c4123 100644 >> --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts >> +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts >> @@ -11,78 +11,9 @@ >> >> aliases { >> serial0 = &uart4; >> - ethernet0 = ðernet0; >> }; >> >> chosen { >> stdout-path = "serial0:115200n8"; >> }; >> - >> - ethernet_vio: vioregulator { >> - compatible = "regulator-fixed"; >> - regulator-name = "vio"; >> - regulator-min-microvolt = <3300000>; >> - regulator-max-microvolt = <3300000>; >> - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; >> - regulator-always-on; >> - regulator-boot-on; >> - }; >> -}; >> - >> -ðernet0 { >> - status = "okay"; >> - pinctrl-0 = <ðernet0_rmii_pins_a>; >> - pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; >> - pinctrl-names = "default", "sleep"; >> - phy-mode = "rmii"; >> - max-speed = <100>; >> - phy-handle = <&phy0>; >> - st,eth_ref_clk_sel; >> - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; >> - >> - mdio0 { >> - #address-cells = <1>; >> - #size-cells = <0>; >> - compatible = "snps,dwmac-mdio"; >> - >> - phy0: ethernet-phy@1 { >> - reg = <1>; >> - }; >> - }; >> -}; >> - >> -&pinctrl { >> - ethernet0_rmii_pins_a: rmii-0 { >> - pins1 { >> - pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ >> - <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ >> - <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ >> - <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ >> - <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ >> - <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ >> - bias-disable; >> - drive-push-pull; >> - slew-rate = <2>; >> - }; >> - pins2 { >> - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ >> - <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ >> - <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ >> - bias-disable; >> - }; >> - }; >> - >> - ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { >> - pins1 { >> - pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ >> - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ >> - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ >> - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ >> - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ >> - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ >> - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ >> - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ >> - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ >> - }; >> - }; >> }; >> diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi >> index b3f4cb4515..643aec94ce 100644 >> --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi >> +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi >> @@ -14,12 +14,23 @@ >> / { >> aliases { >> eeprom0 = &eeprom0; >> + ethernet0 = ðernet0; >> }; >> >> memory@c0000000 { >> device_type = "memory"; >> reg = <0xC0000000 0x40000000>; >> }; >> + >> + ethernet_vio: vioregulator { >> + compatible = "regulator-fixed"; >> + regulator-name = "vio"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; >> + regulator-always-on; >> + regulator-boot-on; >> + }; >> }; >> >> &cec { >> @@ -39,6 +50,28 @@ >> status = "okay"; >> }; >> >> +ðernet0 { >> + status = "okay"; >> + pinctrl-0 = <ðernet0_rmii_pins_a>; >> + pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; >> + pinctrl-names = "default", "sleep"; >> + phy-mode = "rmii"; >> + max-speed = <100>; >> + phy-handle = <&phy0>; >> + st,eth_ref_clk_sel; >> + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; >> + >> + mdio0 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "snps,dwmac-mdio"; >> + >> + phy0: ethernet-phy@1 { >> + reg = <1>; >> + }; >> + }; >> +}; >> + >> &i2c2 { >> pinctrl-names = "default"; >> pinctrl-0 = <&i2c2_pins_a>; >> @@ -228,6 +261,42 @@ >> vdd_3v3_usbfs-supply = <&vdd_usb>; >> }; >> >> +&pinctrl { >> + ethernet0_rmii_pins_a: rmii-0 { >> + pins1 { >> + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ >> + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ >> + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ >> + <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ >> + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ >> + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ >> + bias-disable; >> + drive-push-pull; >> + slew-rate = <2>; >> + }; >> + pins2 { >> + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ >> + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ >> + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ >> + bias-disable; >> + }; >> + }; >> + >> + ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { >> + pins1 { >> + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ >> + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ >> + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ >> + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ >> + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ >> + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ >> + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ >> + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ >> + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ >> + }; >> + }; >> +}; >> + >> &qspi { >> pinctrl-names = "default", "sleep"; >> pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; > Reviewed-by: Patrice Chotard <patrice.chotard@st.com> > > Thanks > > Patrice Applied to u-boot-stm/master Thanks Patrice
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts index dd98c7abee..52a77c4123 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts @@ -11,78 +11,9 @@ aliases { serial0 = &uart4; - ethernet0 = ðernet0; }; chosen { stdout-path = "serial0:115200n8"; }; - - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - max-speed = <100>; - phy-handle = <&phy0>; - st,eth_ref_clk_sel; - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&pinctrl { - ethernet0_rmii_pins_a: rmii-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ - <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ - <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ - <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ - <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ - bias-disable; - }; - }; - - ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ - }; - }; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index b3f4cb4515..643aec94ce 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -14,12 +14,23 @@ / { aliases { eeprom0 = &eeprom0; + ethernet0 = ðernet0; }; memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x40000000>; }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + }; }; &cec { @@ -39,6 +50,28 @@ status = "okay"; }; +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth_ref_clk_sel; + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; @@ -228,6 +261,42 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; }; +&pinctrl { + ethernet0_rmii_pins_a: rmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; +}; + &qspi { pinctrl-names = "default", "sleep"; pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
The PHY and the VIO regulator is populated on the SoM, move it into the SoM DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> --- arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 69 ------------------------- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 69 +++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 69 deletions(-)