| Message ID | 20200721110145.58472-1-wolfgang.wallner@br-automation.com |
|---|---|
| State | Accepted |
| Commit | 491135805e087d4aa05aed1c53722154d8ec5ad2 |
| Delegated to: | Bin Meng |
| Headers | show |
| Series | x86: irq: Fix some typos | expand |
On Tue, Jul 21, 2020 at 7:01 PM Wolfgang Wallner <wolfgang.wallner@br-automation.com> wrote: > > Fix some typos in arch/x86/include/asm/irq.h. > > Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> > > --- > > arch/x86/include/asm/irq.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On Tue, Jul 21, 2020 at 8:37 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Tue, Jul 21, 2020 at 7:01 PM Wolfgang Wallner > <wolfgang.wallner@br-automation.com> wrote: > > > > Fix some typos in arch/x86/include/asm/irq.h. > > > > Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> > > > > --- > > > > arch/x86/include/asm/irq.h | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> applied to u-boot-x86, thanks!
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index e5c916070c..bee0760c2d 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -12,8 +12,8 @@ * Intel interrupt router configuration mechanism * * There are two known ways of Intel interrupt router configuration mechanism - * so far. On most cases, the IRQ routing configuraiton is controlled by PCI - * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). + * so far. On most cases, the IRQ routing configuration is controlled by PCI + * configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0). * On some newer platforms like BayTrail and Braswell, the IRQ routing is now * in the IBASE register block where IBASE is memory-mapped. */ @@ -36,7 +36,7 @@ struct pirq_regmap { * @link_base: link value base number * @link_num: number of PIRQ links supported * @has_regmap: has mapping table between PIRQ link and routing register offset - * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means + * @irq_mask: IRQ mask representing the 16 IRQs in 8259, bit N is 1 means * IRQ N is available to be routed * @lb_bdf: irq router's PCI bus/device/function number encoding * @ibase: IBASE register block base address
Fix some typos in arch/x86/include/asm/irq.h. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> --- arch/x86/include/asm/irq.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)