Message ID | 20200710004012.3016230-7-sjg@chromium.org |
---|---|
State | Superseded |
Delegated to: | Simon Glass |
Headers | show
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[73.14.175.90]) by smtp.gmail.com with ESMTPSA id s18sm2554439ilj.63.2020.07.09.17.40.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 17:40:58 -0700 (PDT) From: Simon Glass <sjg@chromium.org> To: U-Boot Mailing List <u-boot@lists.denx.de> Cc: Simon Glass <sjg@chromium.org>, Bin Meng <bmeng.cn@gmail.com>, Jagan Teki <jagan@amarulasolutions.com>, huang lin <hl@rock-chips.com>, Jeffy Chen <jeffy.chen@rock-chips.com>, Kever Yang <kever.yang@rock-chips.com>, Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Subject: [PATCH v3 27/49] rockchip: bob: Support SPI-flash booting Date: Thu, 9 Jul 2020 18:39:50 -0600 Message-Id: <20200710004012.3016230-7-sjg@chromium.org> X-Mailer: git-send-email 2.27.0.389.gc38d7665816-goog In-Reply-To: <20200710004012.3016230-1-sjg@chromium.org> References: <20200710004012.3016230-1-sjg@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <https://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean |
Series |
rockchip: x86: Support building ROM files automatically with binman
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diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index dad96d2ad1..4ffc33398a 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 @@ -40,6 +40,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -53,6 +54,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y
Update the config for chromebook_bob to support booting from SPI flash. The existing SPL size is too small since ATF is needed, so double it. Signed-off-by: Simon Glass <sjg@chromium.org> --- (no changes since v1) configs/chromebook_bob_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)