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[v2,5/5] mips: octeon: Add empty invalidate_dcache_range()

Message ID 20200630103320.1290545-6-sr@denx.de
State New
Delegated to: Daniel Schwierzeck
Headers show
Series mips: Improve initial Octeon MIPS64 support | expand

Commit Message

Stefan Roese June 30, 2020, 10:33 a.m. UTC
As Octeon is cache coherent, lets add an empty version of
invalidate_dcache_range(). With this, all global cache functions
are replaced by no-ops on Octeon.

Signed-off-by: Stefan Roese <sr@denx.de>

---

(no changes since v1)

 arch/mips/mach-octeon/cache.c | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c
index bea846d757..9a88bb97c7 100644
--- a/arch/mips/mach-octeon/cache.c
+++ b/arch/mips/mach-octeon/cache.c
@@ -18,3 +18,7 @@  void flush_dcache_range(ulong start_addr, ulong stop)
 void flush_cache(ulong start_addr, ulong size)
 {
 }
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+}