diff mbox series

[v2,3/5] mips: octeon: octeon_ebb7304: Change TEXT_BASE to L2 cache

Message ID 20200630103320.1290545-4-sr@denx.de
State New
Delegated to: Daniel Schwierzeck
Headers show
Series mips: Improve initial Octeon MIPS64 support | expand

Commit Message

Stefan Roese June 30, 2020, 10:33 a.m. UTC
Change the linking address (TEXT_BASE) to point to the L2 cache. This
way, mips_mach_early_init() will copy itself into L2 cache and run from
there to improve the bootup speed.

Also CONFIG_MIPS_CACHE_SETUP needs to be disabled, as now the cache is
used at this time and can't be resetted.

Signed-off-by: Stefan Roese <sr@denx.de>
---

(no changes since v1)

 configs/octeon_ebb7304_defconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig
index 0304b1ef8d..dc80fba848 100644
--- a/configs/octeon_ebb7304_defconfig
+++ b/configs/octeon_ebb7304_defconfig
@@ -1,5 +1,5 @@ 
 CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xffffffffbfc00000
+CONFIG_SYS_TEXT_BASE=0xffffffff80000000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -7,6 +7,7 @@  CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEBUG_UART_BASE=0x8001180000000800
 CONFIG_DEBUG_UART_CLOCK=1200000000
 CONFIG_ARCH_OCTEON=y
+# CONFIG_MIPS_CACHE_SETUP is not set
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_HUSH_PARSER=y