diff mbox series

arm: socfpga: misc_s10: Fix EMAC register address calculation

Message ID 20200625113547.100829-1-ley.foon.tan@intel.com
State Accepted
Commit 8a204312abad7913f9b2209a71bef81853647b21
Delegated to: Simon Goldschmidt
Headers show
Series arm: socfpga: misc_s10: Fix EMAC register address calculation | expand

Commit Message

Tan, Ley Foon June 25, 2020, 11:35 a.m. UTC
Fix EMAC register address calculation, address need to multiply
with sizeof(u32) or 4.

This fixes write to invalid address.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/misc_s10.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index ccff78a2307f..670bfa1a31fd 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -68,7 +68,7 @@  static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
 		return -EINVAL;
 
 	clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
-			gmac_index,
+			(gmac_index * sizeof(u32)),
 			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
 
 	return 0;