diff mbox series

arm: socfpga: gen5: Enable cache driver in SPL

Message ID 20200605082009.175720-1-ley.foon.tan@intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series arm: socfpga: gen5: Enable cache driver in SPL | expand

Commit Message

Tan, Ley Foon June 5, 2020, 8:20 a.m. UTC
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
to enable cache driver in SPL.

This fixed error below in SPL:
cache controller driver NOT found!

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/dts/socfpga-common-u-boot.dtsi | 4 ++++
 arch/arm/mach-socfpga/Kconfig           | 1 +
 2 files changed, 5 insertions(+)

Comments

Marek Vasut June 5, 2020, 12:52 p.m. UTC | #1
On 6/5/20 10:20 AM, Ley Foon Tan wrote:
> Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
> to enable cache driver in SPL.
> 
> This fixed error below in SPL:
> cache controller driver NOT found!
> 
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Is this for current release or next ?
Simon Goldschmidt June 5, 2020, 8:15 p.m. UTC | #2
Marek Vasut <marex@denx.de> schrieb am Fr., 5. Juni 2020, 14:52:

> On 6/5/20 10:20 AM, Ley Foon Tan wrote:
> > Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
> > to enable cache driver in SPL.
> >
> > This fixed error below in SPL:
> > cache controller driver NOT found!
>

What's the size impact of this? What is the actual problem? From this
description, I would think the message needs to be fixed instead of adding
cache drivers?

We're already quite constrained in gen5. I'm not keen on adding drivers
just because of an error message...

Regards,
Simon

>
> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>
> Is this for current release or next ?
>
Tan, Ley Foon June 9, 2020, 9:52 a.m. UTC | #3
> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Friday, June 5, 2020 8:53 PM
> To: Tan, Ley Foon <ley.foon.tan@intel.com>; u-boot@lists.denx.de
> Cc: Ley Foon Tan <lftan.linux@gmail.com>; See, Chin Liang
> <chin.liang.see@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Ang, Chee Hong
> <chee.hong.ang@intel.com>
> Subject: Re: [PATCH] arm: socfpga: gen5: Enable cache driver in SPL
> 
> On 6/5/20 10:20 AM, Ley Foon Tan wrote:
> > Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE to enable
> > cache driver in SPL.
> >
> > This fixed error below in SPL:
> > cache controller driver NOT found!
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> 
> Is this for current release or next ?
Can drop this patch first. Just found out only see this error when enable ECC scrubbing with Dcache in Gen5 in our downstream branch. But, mainline Uboot haven't support ECC in Gen5 yet. Will add this patch when enable ECC in Gen5 later.

Thanks.

Regards
Ley Foon
diff mbox series

Patch

diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
index d55460755fe3..f65aca6ebaba 100644
--- a/arch/arm/dts/socfpga-common-u-boot.dtsi
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -14,6 +14,10 @@ 
 	u-boot,dm-pre-reloc;
 };
 
+&L2 {
+	u-boot,dm-pre-reloc;
+};
+
 &rst {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a3699e82a19e..1173422b8f28 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -67,6 +67,7 @@  config TARGET_SOCFPGA_CYCLONE5
 config TARGET_SOCFPGA_GEN5
 	bool
 	select SPL_ALTERA_SDRAM
+	select SPL_CACHE if SPL
 	imply FPGA_SOCFPGA
 	imply SPL_SIZE_LIMIT_SUBTRACT_GD
 	imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC