@@ -1599,7 +1599,6 @@ source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
-source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t102xqds/Kconfig"
source "board/freescale/t102xrdb/Kconfig"
deleted file mode 100644
@@ -1,14 +0,0 @@
-if TARGET_P2041RDB
-
-config SYS_BOARD
- default "p2041rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P2041RDB"
-
-source "board/freescale/common/Kconfig"
-
-endif
deleted file mode 100644
@@ -1,11 +0,0 @@
-P2041RDB BOARD
-#M: -
-S: Maintained
-F: board/freescale/p2041rdb/
-F: include/configs/P2041RDB.h
-F: configs/P2041RDB_defconfig
-F: configs/P2041RDB_NAND_defconfig
-F: configs/P2041RDB_SDCARD_defconfig
-F: configs/P2041RDB_SECURE_BOOT_defconfig
-F: configs/P2041RDB_SPIFLASH_defconfig
-F: configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2011 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += p2041rdb.o
-obj-y += cpld.o
-obj-y += ddr.o
-obj-y += eth.o
deleted file mode 100644
@@ -1,141 +0,0 @@
-Overview
-=========
-The P2041 Processor combines four Power Architecture processor cores
-with high-performance datapath acceleration architecture(DPAA), CoreNet
-fabric infrastructure, as well as network and peripheral bus interfaces
-required for networking, telecom/datacom, wireless infrastructure, and
-military/aerospace applications.
-
-P2041RDB board is a quad core platform supporting the P2041 processor
-of QorIQ DPAA series.
-
-Boot from NOR flash
-===================
-1. Build image
- make P2041RDB_config
- make all
-
-2. Program image
- => tftp 1000000 u-boot.bin
- => protect off all
- => erase eff40000 efffffff
- => cp.b 1000000 eff40000 c0000
-
-3. Program RCW
- => tftp 1000000 rcw.bin
- => protect off all
- => erase e8000000 e801ffff
- => cp.b 1000000 e8000000 50
-
-4. Program FMAN Firmware ucode
- => tftp 1000000 ucode.bin
- => protect off all
- => erase eff00000 eff3ffff
- => cp.b 1000000 eff00000 2000
-
-5. Change DIP-switch
- SW1[1-5] = 10110
- Note: 1 stands for 'on', 0 stands for 'off'
-
-Boot from SDCard
-===================
-1. Build image
- make P2041RDB_SDCARD_config
- make all
-
-2. Generate PBL imge
- Use PE tool to produce a image used to be programed to
- SDCard which contains RCW and U-Boot image.
-
-3. Program the PBL image to SDCard
- => tftp 1000000 pbl_sd.bin
- => mmcinfo
- => mmc write 1000000 8 672
-
-4. Program FMAN Firmware ucode
- => tftp 1000000 ucode.bin
- => mmc write 1000000 690 10
-
-5. Change DIP-switch
- SW1[1-5] = 01100
- Note: 1 stands for 'on', 0 stands for 'off'
-
-Boot from SPI flash
-===================
-1. Build image
- make P2041RDB_SPIFLASH_config
- make all
-
-2. Generate PBL imge
- Use PE tool to produce a image used to be programed to
- SPI flash which contains RCW and U-Boot image.
-
-3. Program the PBL image to SPI flash
- => tftp 1000000 pbl_spi.bin
- => spi probe 0
- => sf erase 0 100000
- => sf write 1000000 0 $filesize
-
-4. Program FMAN Firmware ucode
- => tftp 1000000 ucode.bin
- => sf erase 110000 10000
- => sf write 1000000 110000 $filesize
-
-5. Change DIP-switch
- SW1[1-5] = 10100
- Note: 1 stands for 'on', 0 stands for 'off'
-
-Device tree support and how to enable it for different configs
---------------------------------------------------------------
-Device tree support is available for p2041rdb for below mentioned boot,
-1. NOR Boot
-2. NAND Boot
-3. SD Boot
-4. SPIFLASH Boot
-
-To enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
-2. CONFIG_OF_CONTROL
-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
- CONFIG_RESET_VECTOR_ADDRESS - 0xffc
-
-If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin'
-instead of u-boot.bin for all boot.
-
-CPLD command
-============
-The CPLD is used to control the power sequence and some serdes lane
-mux function.
-
-cpld reset - hard reset to default bank
-cpld reset altbank - reset to alternate bank
-cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
- lane 6: 0 -> slot1 (Default)
- 1 -> SGMII
- lane a: 0 -> slot2 (Default)
- 1 -> AURORA
- lane c: 0 -> slot2 (Default)
- 1 -> SATA0
- lane d: 0 -> slot2 (Default)
- 1 -> SATA1
-
-Using the Device Tree Source File
-=================================
-To create the DTB (Device Tree Binary) image file, use a command
-similar to this:
- dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
-
-Or use the following command:
- {linux-2.6}/make p2041rdb.dtb ARCH=powerpc
-
-then the dtb file will be generated under the following directory:
- {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
-
-Booting Linux
-=============
-Place a linux uImage in the TFTP disk area.
- tftp 1000000 uImage
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp 3000000 p2041rdb.dtb
- bootm 1000000 2000000 3000000
deleted file mode 100644
@@ -1,157 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2011 Freescale Semiconductor
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- *
- * This file provides support for the board-specific CPLD used on some Freescale
- * reference boards.
- *
- * The following macros need to be defined:
- *
- * CPLD_BASE - The virtual address of the base of the CPLD register map
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#include "cpld.h"
-
-static u8 __cpld_read(unsigned int reg)
-{
- void *p = (void *)CPLD_BASE;
-
- return in_8(p + reg);
-}
-u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
-
-static void __cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CPLD_BASE;
-
- out_8(p + reg, value);
-}
-void cpld_write(unsigned int reg, u8 value)
- __attribute__((weak, alias("__cpld_write")));
-
-/*
- * Reset the board. This honors the por_cfg registers.
- */
-void __cpld_reset(void)
-{
- CPLD_WRITE(system_rst, 1);
-}
-void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
-
-/**
- * Set the boot bank to the alternate bank
- */
-void __cpld_set_altbank(void)
-{
- u8 reg5 = CPLD_READ(sw_ctl_on);
-
- CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
- CPLD_WRITE(fbank_sel, 1);
- CPLD_WRITE(system_rst, 1);
-}
-void cpld_set_altbank(void)
- __attribute__((weak, alias("__cpld_set_altbank")));
-
-/**
- * Set the boot bank to the default bank
- */
-void __cpld_set_defbank(void)
-{
- CPLD_WRITE(system_rst_default, 1);
-}
-void cpld_set_defbank(void)
- __attribute__((weak, alias("__cpld_set_defbank")));
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
- printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
- printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver));
- printf("system_rst = 0x%02x\n", CPLD_READ(system_rst));
- printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on));
- printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg));
- printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe));
- printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel));
- printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk));
- printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk));
- printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel));
- printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux));
- printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2)));
- putc('\n');
-}
-#endif
-
-int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else
- cpld_set_defbank();
- } else if (strcmp(argv[1], "lane_mux") == 0) {
- u32 lane = simple_strtoul(argv[2], NULL, 16);
- u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
- u8 reg = CPLD_READ(serdes_mux);
-
- switch (lane) {
- case 0x6:
- reg &= ~SERDES_MUX_LANE_6_MASK;
- reg |= val << SERDES_MUX_LANE_6_SHIFT;
- break;
- case 0xa:
- reg &= ~SERDES_MUX_LANE_A_MASK;
- reg |= val << SERDES_MUX_LANE_A_SHIFT;
- break;
- case 0xc:
- reg &= ~SERDES_MUX_LANE_C_MASK;
- reg |= val << SERDES_MUX_LANE_C_SHIFT;
- break;
- case 0xd:
- reg &= ~SERDES_MUX_LANE_D_MASK;
- reg |= val << SERDES_MUX_LANE_D_SHIFT;
- break;
- default:
- printf("Invalid value\n");
- break;
- }
-
- CPLD_WRITE(serdes_mux, reg);
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else
- rc = cmd_usage(cmdtp);
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
- "Reset the board or pin mulexing selection using the CPLD sequencer",
- "reset - hard reset to default bank\n"
- "cpld_cmd reset altbank - reset to alternate bank\n"
- "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
- " lane 6: 0 -> slot1\n"
- " 1 -> SGMII (Default)\n"
- " lane a: 0 -> slot2\n"
- " 1 -> AURORA (Default)\n"
- " lane c: 0 -> slot2\n"
- " 1 -> SATA0 (Default)\n"
- " lane d: 0 -> slot2\n"
- " 1 -> SATA1 (Default)\n"
-#ifdef DEBUG
- "cpld_cmd dump - display the CPLD registers\n"
-#endif
- );
deleted file mode 100644
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2011 Freescale Semiconductor
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/*
- * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
- */
-typedef struct cpld_data {
- u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
- u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
- u8 pcba_ver; /* 0x2 - PCBA Revision Register */
- u8 system_rst; /* 0x3 - system reset register */
- u8 res0; /* 0x4 - not used */
- u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */
- u8 por_cfg; /* 0x6 - POR Control Register */
- u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */
- u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */
- u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */
- u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */
- u8 fbank_sel; /* 0xb - Flash bank selection */
- u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */
- u8 sw[1]; /* 0xd - SW2 Status */
- u8 system_rst_default; /* 0xe - system reset to default register */
- u8 sysclk_sw1; /* 0xf - sysclk configuration register */
-} __attribute__ ((packed)) cpld_data_t;
-
-#define SERDES_MUX_LANE_6_MASK 0x2
-#define SERDES_MUX_LANE_6_SHIFT 1
-#define SERDES_MUX_LANE_A_MASK 0x1
-#define SERDES_MUX_LANE_A_SHIFT 0
-#define SERDES_MUX_LANE_C_MASK 0x4
-#define SERDES_MUX_LANE_C_SHIFT 2
-#define SERDES_MUX_LANE_D_MASK 0x8
-#define SERDES_MUX_LANE_D_SHIFT 3
-#define CPLD_SWITCH_BANK_ENABLE 0x40
-#define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */
-#define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */
-
-/* Pointer to the CPLD register set */
-#define cpld ((cpld_data_t *)CPLD_BASE)
-
-/* The CPLD SW register that corresponds to board switch X, where x >= 1 */
-#define CPLD_SW(x) (cpld->sw[(x) - 2])
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg))
-#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)
deleted file mode 100644
@@ -1,143 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- *
- * ranges for parameters:
- * wr_data_delay = 0-6
- * clk adjust = 0-8
- * cpo 2-0x1E (30)
- */
-static const struct board_specific_parameters dimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | delay|
- */
- {2, 750, 3, 5, 0xff, 2, 0},
- {2, 1250, 4, 6, 0xff, 2, 0},
- {2, 1350, 5, 7, 0xff, 2, 0},
- {2, 1666, 5, 8, 0xff, 2, 0},
- {}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = dimm0;
-
- /*
- * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /* Write leveling override */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /* Rtt and Rtt_WR override */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 60 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing....");
-
- if (fsl_use_spd()) {
- puts("using SPD\n");
- dram_size = fsl_ddr_sdram();
- } else {
- puts("no SPD and fixed parameters\n");
- return -ENXIO;
- }
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
deleted file mode 100644
@@ -1,201 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- */
-
-/*
- * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
- * are provided by the three on-board PHY or by the standard Freescale
- * four-port SGMII riser card. We need to change the phy-handle in the
- * kernel dts file to point to the correct PHY according to serdes mux
- * and serdes protocol selection.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-
-#include "cpld.h"
-#include "../common/fman.h"
-
-#ifdef CONFIG_FMAN_ENET
-/*
- * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot
- */
-static u8 lane_to_slot[] = {
- 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
-};
-
-static int riser_phy_addr[] = {
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
-};
-
-/*
- * Initialize the lane_to_slot[] array.
- *
- * On the P2040RDB board the mapping is controlled by CPLD register.
- */
-static void initialize_lane_to_slot(void)
-{
- u8 mux = CPLD_READ(serdes_mux);
-
- lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
- lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
- lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
- lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
-}
-
-/*
- * Given the following ...
- *
- * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
- * compatible string and 'addr' physical address)
- *
- * 2) An Fman port
- *
- * ... update the phy-handle property of the Ethernet node to point to the
- * right PHY. This assumes that we already know the PHY for each port.
- *
- * The offset of the Fman Ethernet node is also passed in for convenience, but
- * it is not used, and we recalculate the offset anyway.
- *
- * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
- * Inside the Fman, "ports" are things that connect to MACs. We only call them
- * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
- * and ports are the same thing.
- *
- */
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- phy_interface_t intf = fm_info_get_enet_if(port);
- char phy[16];
-
- /* The RGMII PHY is identified by the MAC connected to it */
- if (intf == PHY_INTERFACE_MODE_RGMII) {
- sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
-
- /* The SGMII PHY is identified by the MAC connected to it */
- if (intf == PHY_INTERFACE_MODE_SGMII) {
- int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
- u8 slot;
- if (lane < 0)
- return;
- slot = lane_to_slot[lane];
- if (slot) {
- sprintf(phy, "phy_sgmii_%x",
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
- + (port - FM1_DTSEC1));
- fdt_set_phy_handle(fdt, compat, addr, phy);
- } else {
- sprintf(phy, "phy_sgmii_%x",
- CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
- + (port - FM1_DTSEC1));
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
- }
-
- if (intf == PHY_INTERFACE_MODE_XGMII) {
- /* XAUI */
- int lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0) {
- /* The XAUI PHY is identified by the slot */
- sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
- }
-}
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct fsl_pq_mdio_info dtsec_mdio_info;
- struct tgec_mdio_info tgec_mdio_info;
- unsigned int i, slot;
- int lane;
-
- printf("Initializing Fman\n");
-
- initialize_lane_to_slot();
-
- dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the real 10G MDIO bus */
- fm_tgec_mdio_init(bis, &tgec_mdio_info);
-
- /*
- * Program the three on-board SGMII PHY addresses. If the SGMII Riser
- * card used, we'll override the PHY address later. For any DTSEC that
- * is RGMII, we'll also override its PHY address later. We assume that
- * DTSEC4 and DTSEC5 are used for RGMII.
- */
- fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- if (slot)
- fm_info_set_phy_address(i, riser_phy_addr[i]);
- break;
- case PHY_INTERFACE_MODE_RGMII:
- /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
- fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
- CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
- break;
- default:
- printf("Fman1: DTSEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- break;
- }
-
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
- }
-
- lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0) {
- slot = lane_to_slot[lane];
- if (slot)
- fm_info_set_phy_address(FM1_10GEC1,
- CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
- }
-
- fm_info_set_mdio(FM1_10GEC1,
- miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
deleted file mode 100644
@@ -1,244 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011,2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-extern void pci_of_setup(void *blob, bd_t *bd);
-
-#include "cpld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- u8 sw;
- struct cpu_type *cpu = gd->arch.cpu;
- unsigned int i;
-
- printf("Board: %sRDB, ", cpu->name);
- printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
- CPLD_READ(cpld_ver_sub));
-
- sw = CPLD_READ(fbank_sel);
- printf("vBank: %d\n", sw & 0x1);
-
- /*
- * Display the actual SERDES reference clocks as configured by the
- * dip switches on the board. Note that the SWx registers could
- * technically be set to force the reference clocks to match the
- * values that the SERDES expects (or vice versa). For now, however,
- * we just display both values and hope the user notices when they
- * don't match.
- */
- puts("SERDES Reference Clocks: ");
- sw = in_8(&CPLD_SW(2)) >> 2;
- for (i = 0; i < 2; i++) {
- static const char * const freq[][3] = {{"0", "100", "125"},
- {"100", "156.25", "125"}
- };
- unsigned int clock = (sw >> (2 * i)) & 3;
-
- printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
- }
- puts("\n");
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
- setbits_be32(&gur->ddrclkdr, 0x000f000f);
-
- return 0;
-}
-
-#define CPLD_LANE_A_SEL 0x1
-#define CPLD_LANE_G_SEL 0x2
-#define CPLD_LANE_C_SEL 0x4
-#define CPLD_LANE_D_SEL 0x8
-
-void board_config_lanes_mux(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
- u8 mux = 0;
- switch (srds_prtcl) {
- case 0x2:
- case 0x5:
- case 0x9:
- case 0xa:
- case 0xf:
- break;
- case 0x8:
- mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
- break;
- case 0x14:
- mux |= CPLD_LANE_A_SEL;
- break;
- case 0x17:
- mux |= CPLD_LANE_G_SEL;
- break;
- case 0x16:
- case 0x19:
- case 0x1a:
- mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
- break;
- case 0x1c:
- mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
- break;
- default:
- printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
- break;
- }
- CPLD_WRITE(serdes_mux, mux);
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- board_config_lanes_mux();
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(unsigned long dummy)
-{
- u8 sysclk_conf = CPLD_READ(sysclk_sw1);
-
- switch (sysclk_conf & 0x7) {
- case CPLD_SYSCLK_83:
- return 83333333;
- case CPLD_SYSCLK_100:
- return 100000000;
- default:
- return 66666666;
- }
-}
-
-#define NUM_SRDS_BANKS 2
-
-int misc_init_r(void)
-{
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 actual[NUM_SRDS_BANKS];
- unsigned int i;
- u8 sw;
- static const int freq[][3] = {
- {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
- {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
- SRDS_PLLCR0_RFCK_SEL_125}
- };
-
- sw = in_8(&CPLD_SW(2)) >> 2;
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- unsigned int clock = (sw >> (2 * i)) & 3;
- if (clock == 0x3) {
- printf("Warning: SDREFCLK%u switch setting of '11' is "
- "unsupported\n", i + 1);
- break;
- }
- if (i == 0 && clock == 0)
- puts("Warning: SDREFCLK1 switch setting of"
- "'00' is unsupported\n");
- else
- actual[i] = freq[i][clock];
-
- /*
- * PC board uses a different CPLD with PB board, this CPLD
- * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
- * board has cpld_ver_sub = 0, and pcba_ver = 4.
- */
- if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
- (CPLD_READ(pcba_ver) == 5)) {
- /* PC board bank2 frequency */
- actual[i] = freq[i-1][clock];
- }
- }
-
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- u32 expected = in_be32(®s->bank[i].pllcr0);
- expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
- if (expected != actual[i]) {
- printf("Warning: SERDES bank %u expects reference clock"
- " %sMHz, but actual is %sMHz\n", i + 1,
- serdes_clock_to_string(expected),
- serdes_clock_to_string(actual[i]));
- }
- }
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
-#endif
-
- return 0;
-}
deleted file mode 100644
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
deleted file mode 100644
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
deleted file mode 100644
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
deleted file mode 100644
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
deleted file mode 100644
@@ -1,50 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
deleted file mode 100644
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
deleted file mode 100644
@@ -1,585 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * P2041 RDB board configuration file
- * Also supports P2040 RDB
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
-#endif
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_SYS_DPAA_RMAN /* RMan */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
- #define CONFIG_FSL_FIXED_MMC_LOCATION
- #define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(unsigned long dummy);
-#include <linux/stringify.h>
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
- CONFIG_RAMBOOT_TEXT_BASE)
-#else
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
-#endif
-#define CONFIG_SYS_L3_SIZE (1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x52
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * Local Bus Definitions
- */
-
-/* Set the local bus clock 1/8 of platform clock */
-#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
-
-/*
- * This board doesn't have a promjet connector.
- * However, it uses commone corenet board LAW and TLB.
- * It is necessary to use the same start address with proper offset.
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
- BR_PS_16 | BR_V)
-#define CONFIG_SYS_FLASH_OR_PRELIM \
- ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
- | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
-
-#define CONFIG_FSL_CPLD
-#define CPLD_BASE 0xffdf0000 /* CPLD registers */
-#ifdef CONFIG_PHYS_64BIT
-#define CPLD_BASE_PHYS 0xfffdf0000ull
-#else
-#define CPLD_BASE_PHYS CPLD_BASE
-#endif
-
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
-#define PIXIS_LBMAP_SWITCH 7
-#define PIXIS_LBMAP_MASK 0xf0
-#define PIXIS_LBMAP_SHIFT 4
-#define PIXIS_LBMAP_ALTBANK 0x40
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_NAND_FSL_ELBC
-/* Nand Flash */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#endif /* CONFIG_NAND_FSL_ELBC */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_FSL
-
-
-/*
- * RapidIO
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
-#endif
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
-
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-
-/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
-#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#define CONFIG_FSL_SATA_V2
-
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
-#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
-#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
-#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
-
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
-
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
-
-#define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_ETHPRIME "FM1@DTSEC1"
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Command line configuration.
- */
-
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_HAS_FSL_MPH_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
- "bank_intlv=cs0_cs1\0" \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
- "usb_dr_mode=host\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=p2041rdb/p2041rdb.dtb\0" \
- "bdev=sda3\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
This board has not been converted to CONFIG_DM_SPI by the deadline. Remove it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- arch/powerpc/cpu/mpc85xx/Kconfig | 1 - board/freescale/p2041rdb/Kconfig | 14 - board/freescale/p2041rdb/MAINTAINERS | 11 - board/freescale/p2041rdb/Makefile | 10 - board/freescale/p2041rdb/README | 141 ------ board/freescale/p2041rdb/cpld.c | 157 ------ board/freescale/p2041rdb/cpld.h | 54 -- board/freescale/p2041rdb/ddr.c | 143 ------ board/freescale/p2041rdb/eth.c | 201 -------- board/freescale/p2041rdb/p2041rdb.c | 244 --------- configs/P2041RDB_NAND_defconfig | 64 --- configs/P2041RDB_SDCARD_defconfig | 63 --- configs/P2041RDB_SECURE_BOOT_defconfig | 57 --- configs/P2041RDB_SPIFLASH_defconfig | 64 --- configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 50 -- configs/P2041RDB_defconfig | 62 --- include/configs/P2041RDB.h | 585 ---------------------- 17 files changed, 1921 deletions(-) delete mode 100644 board/freescale/p2041rdb/Kconfig delete mode 100644 board/freescale/p2041rdb/MAINTAINERS delete mode 100644 board/freescale/p2041rdb/Makefile delete mode 100644 board/freescale/p2041rdb/README delete mode 100644 board/freescale/p2041rdb/cpld.c delete mode 100644 board/freescale/p2041rdb/cpld.h delete mode 100644 board/freescale/p2041rdb/ddr.c delete mode 100644 board/freescale/p2041rdb/eth.c delete mode 100644 board/freescale/p2041rdb/p2041rdb.c delete mode 100644 configs/P2041RDB_NAND_defconfig delete mode 100644 configs/P2041RDB_SDCARD_defconfig delete mode 100644 configs/P2041RDB_SECURE_BOOT_defconfig delete mode 100644 configs/P2041RDB_SPIFLASH_defconfig delete mode 100644 configs/P2041RDB_SRIO_PCIE_BOOT_defconfig delete mode 100644 configs/P2041RDB_defconfig delete mode 100644 include/configs/P2041RDB.h