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Mon, 25 May 2020 11:40:13 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com Cc: marex@denx.de, bmeng.cn@gmail.com, james.quinlan@broadcom.com, sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v4 3/9] pci: Move some PCIe register offset definitions to a common header Date: Mon, 25 May 2020 13:39:53 +0200 Message-Id: <20200525113959.11886-4-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200525113959.11886-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTYRjG+zyXHVeT03Hol0rmKkIlL+UfJzQzCDoRWaF/RJa28uAlb2xq WViTQktNlyu0qXNJYM3L1K2h6cJWXmipGYpKXkBlqMyM0iIVzXm0/vu9z/s83wMvH4FQ5ZgL EZeUykqSxAkinI8aOv70HlTVmSP92hsouqFEi9FP86Noo7UQp4eWsjG69sMoj7ZmZwFarZjC aIOyCqffW3Mw+pfeAOg540NeyHZGOd6NM6WyPpRRKbtQplk5ymO6R5oAU6DXAEarH0AZnfn2 OeIiPyiaTYhLZyW+wVf4sYoyj5TiXTcnn68BGbAIc4E9AckAWKobxXMBn6DIlwC2WvpRblgA cGawlccNPwFcWVXhWxF1TYkdt6gCcLmiGv8XKZ/OAzYXTvrDR+0FGywkveFwjWEjgZCzAFq+ GzHbwpG8BFs0b9cLCQIl98Mn6vM2FJCBcKCN4crcYXV9G2JjezIIfnw3htiegWQlD37rq+dx phOwV65COHaEs536Td0NmhX5KBe4B2B+y1ceN8gBHO9UA84VCEd6lnBbM0J6Qu0bX04+DmsV zZhNhqQDHJrbaZORdSwyFCOcLIAPsinOvQ8ua4rtOHaBeVNrKMcMtNSPbZ60EMAJxRomB+7K /2VqADTAmU2TJsawUv8k9oaPVJwoTUuK8bmWnNgI1j+NebXzRxNY/HLVBEgCiHYI6BpzJIWJ 06UZiSYACUQkFGSfXJcE0eKMW6wkOUqSlsBKTcCVQEXOgsOVM5cpMkacyl5n2RRWsrW1I+xd ZCBUnnXHoeLo3jxKxZtbyNRl/jZZ+enPXvFrh+Pnd39y6woIHm2Mv79SGt722tXoF3SXcgnv OJAwceSFXNc8Pznw2FcrD6vzLvpsdDeumco8NIPKqgbh2dP922RhZ+xO7YlwsiwKQvSSY4ec 5rs6prN6ZBGA6vbyLAGhYxe0qTkiVBor9vdCJFLxX6GU0dwwAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRmVeSWpSXmKPExsVy+t/xu7pz152OM9j80Mxi44z1rBZTe+It 9r7pZ7O48auN1WLtkbvsFm/aGhktFkx+wmqxbdZyNovDb9pZLb5t2cZo8XZvJ7sDt8es+2fZ PGY3XGTxmDfrBIvHzll32T3O3tnB6NG3ZRWjx/otV1k8Np+uDuCI0rMpyi8tSVXIyC8usVWK NrQw0jO0tNAzMrHUMzQ2j7UyMlXSt7NJSc3JLEst0rdL0MuYPEexYLpkxeOF/xkbGJ+JdDFy ckgImEgsWDODCcQWEljKKHGn06eLkQMoLiUxv0UJokRY4s+1LrYuRi6gkk+MEqfu3WcBSbAJ GEr0Hu1jBLFFBHQlGnvWsYAUMQt8YZTYdGAxG8ggYYEoiafL7UFMFgFViSkLAkFMXgFriasH PCDGy0us3nCAGcTmFLCROHXwHjPENdYSM2c9Y5zAyLeAkWEVo0hqaXFuem6xoV5xYm5xaV66 XnJ+7iZGYLhvO/Zz8w7GSxuDDzEKcDAq8fBarDkdJ8SaWFZcmXuIUYKDWUmEt80dKMSbklhZ lVqUH19UmpNafIjRFOikicxSosn5wFjMK4k3NDU0t7A0NDc2NzazUBLn7RA4GCMkkJ5Ykpqd mlqQWgTTx8TBKdXAKHvPjv1h2cT+nwobZRdPMJ9s+69IcPejNRN3/cmLCPpqtkx9h6Rf1UPO RrdCD+O2jV9OqSxuWx618IHmDq56gRXnshIqHcr317Ad5jJ5oX9liq7uhD+HXLK/TphdzfJU jL1Q7Pr16rXLNk24KbuwVWPanNIEPcbiM8x79imwL9JcudhDPnTLTiWW4oxEQy3mouJEAAzr Do6NAgAA X-CMS-MailID: 20200525114013eucas1p1fd8be56fad4c2331a3b2b4bed48f7a02 X-Msg-Generator: CA X-RootMTR: 20200525114013eucas1p1fd8be56fad4c2331a3b2b4bed48f7a02 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200525114013eucas1p1fd8be56fad4c2331a3b2b4bed48f7a02 References: <20200525113959.11886-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki Reviewed-by: Bin Meng Reviewed-by: Nicolas Saenz Julienne --- Changes since v1: - none. Changes since RFC: - whitespace clean up. --- drivers/pci/pci-rcar-gen3.c | 8 -------- drivers/pci/pcie_intel_fpga.c | 3 --- include/pci.h | 13 +++++++++++-- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 30eff67..393f1c9 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -117,14 +117,6 @@ #define RCAR_PCI_MAX_RESOURCES 4 #define MAX_NR_INBOUND_MAPS 6 -#define PCI_EXP_FLAGS 2 /* Capabilities register */ -#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - enum { RCAR_PCI_ACCESS_READ, RCAR_PCI_ACCESS_WRITE, diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 6a9f29c..69363a0 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -65,9 +65,6 @@ #define IS_ROOT_PORT(pcie, bdf) \ ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) -#define PCI_EXP_LNKSTA 18 /* Link Status */ -#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ - /** * struct intel_fpga_pcie - Intel FPGA PCIe controller state * @bus: Pointer to the PCI bus diff --git a/include/pci.h b/include/pci.h index aff56b2..dfdbb32 100644 --- a/include/pci.h +++ b/include/pci.h @@ -471,10 +471,19 @@ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ /* PCI Express capabilities */ +#define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ -#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ -#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +#define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ /* Include the ID list */