| Message ID | 20200525101949.15944-9-patrick.delaunay@st.com |
|---|---|
| State | Accepted |
| Commit | 4a87fea6de30b6e9c59a5abb6da1d0d84c984d15 |
| Delegated to: | Patrick Delaunay |
| Headers | show |
| Series | stm32mp1: use OPP information for PLL1 settings in SPL | expand |
HI Patrick On 5/25/20 12:19 PM, Patrick Delaunay wrote: > This patch allows to switch the CPU frequency to 800MHz on the > ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM > using the STM32MP15x SOC and when it is supported by the HW > (for STM32MP15xD and STM32MP15xF). > > Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> > --- > > Changes in v2: > - update stm32mp15xx-dhcor and dhcom device tree > > arch/arm/dts/stm32mp15-u-boot.dtsi | 10 ++++++++++ > arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 9 --------- > arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 9 --------- > arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 9 --------- > arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 9 --------- > 5 files changed, 10 insertions(+), 36 deletions(-) > > diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi > index a0d971ad88..66be7df9ae 100644 > --- a/arch/arm/dts/stm32mp15-u-boot.dtsi > +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi > @@ -88,6 +88,16 @@ > u-boot,dm-pre-reloc; > }; > > +&cpu0_opp_table { > + u-boot,dm-spl; > + opp-650000000 { > + u-boot,dm-spl; > + }; > + opp-800000000 { > + u-boot,dm-spl; > + }; > +}; > + > &gpioa { > u-boot,dm-pre-reloc; > }; > diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi > index c52abeb1e7..69cdae6685 100644 > --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi > +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi > @@ -118,15 +118,6 @@ > CLK_LPTIM45_LSE > >; > > - /* VCO = 1300.0 MHz => P = 650 (CPU) */ > - pll1: st,pll@0 { > - compatible = "st,stm32mp1-pll"; > - reg = <0>; > - cfg = < 2 80 0 0 0 PQR(1,0,0) >; > - frac = < 0x800 >; > - u-boot,dm-pre-reloc; > - }; > - > /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ > pll2: st,pll@1 { > compatible = "st,stm32mp1-pll"; > diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi > index 84af7fa47b..3f716306be 100644 > --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi > +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi > @@ -115,15 +115,6 @@ > CLK_LPTIM45_LSE > >; > > - /* VCO = 1300.0 MHz => P = 650 (CPU) */ > - pll1: st,pll@0 { > - compatible = "st,stm32mp1-pll"; > - reg = <0>; > - cfg = < 2 80 0 0 0 PQR(1,0,0) >; > - frac = < 0x800 >; > - u-boot,dm-pre-reloc; > - }; > - > /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ > pll2: st,pll@1 { > compatible = "st,stm32mp1-pll"; > diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi > index 75d75266e8..f96de9e7a3 100644 > --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi > +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi > @@ -235,15 +235,6 @@ > CLK_LPTIM45_LSE > >; > > - /* VCO = 1300.0 MHz => P = 650 (CPU) */ > - pll1: st,pll@0 { > - compatible = "st,stm32mp1-pll"; > - reg = <0>; > - cfg = < 2 80 0 0 0 PQR(1,0,0) >; > - frac = < 0x800 >; > - u-boot,dm-pre-reloc; > - }; > - > /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ > pll2: st,pll@1 { > compatible = "st,stm32mp1-pll"; > diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi > index ef730a8322..4059dabf1d 100644 > --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi > +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi > @@ -105,15 +105,6 @@ > CLK_LPTIM45_LSE > >; > > - /* VCO = 1300.0 MHz => P = 650 (CPU) */ > - pll1: st,pll@0 { > - compatible = "st,stm32mp1-pll"; > - reg = <0>; > - cfg = < 2 80 0 0 0 PQR(1,0,0) >; > - frac = < 0x800 >; > - u-boot,dm-pre-reloc; > - }; > - > /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ > pll2: st,pll@1 { > compatible = "st,stm32mp1-pll"; Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Thanks
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index a0d971ad88..66be7df9ae 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -88,6 +88,16 @@ u-boot,dm-pre-reloc; }; +&cpu0_opp_table { + u-boot,dm-spl; + opp-650000000 { + u-boot,dm-spl; + }; + opp-800000000 { + u-boot,dm-spl; + }; +}; + &gpioa { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index c52abeb1e7..69cdae6685 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -118,15 +118,6 @@ CLK_LPTIM45_LSE >; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - cfg = < 2 80 0 0 0 PQR(1,0,0) >; - frac = < 0x800 >; - u-boot,dm-pre-reloc; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 84af7fa47b..3f716306be 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -115,15 +115,6 @@ CLK_LPTIM45_LSE >; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - cfg = < 2 80 0 0 0 PQR(1,0,0) >; - frac = < 0x800 >; - u-boot,dm-pre-reloc; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 75d75266e8..f96de9e7a3 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -235,15 +235,6 @@ CLK_LPTIM45_LSE >; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - cfg = < 2 80 0 0 0 PQR(1,0,0) >; - frac = < 0x800 >; - u-boot,dm-pre-reloc; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index ef730a8322..4059dabf1d 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -105,15 +105,6 @@ CLK_LPTIM45_LSE >; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - cfg = < 2 80 0 0 0 PQR(1,0,0) >; - frac = < 0x800 >; - u-boot,dm-pre-reloc; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll";
This patch allows to switch the CPU frequency to 800MHz on the ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM using the STM32MP15x SOC and when it is supported by the HW (for STM32MP15xD and STM32MP15xF). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> --- Changes in v2: - update stm32mp15xx-dhcor and dhcom device tree arch/arm/dts/stm32mp15-u-boot.dtsi | 10 ++++++++++ arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 9 --------- arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 9 --------- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 9 --------- arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 9 --------- 5 files changed, 10 insertions(+), 36 deletions(-)