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Mon, 25 May 2020 07:34:44 +0000 From: Pragnesh Patel To: u-boot@lists.denx.de Cc: atish.patra@wdc.com, palmerdabbelt@google.com, bmeng.cn@gmail.com, paul.walmsley@sifive.com, jagan@amarulasolutions.com, anup.patel@wdc.com, sagar.kadam@sifive.com, rick@andestech.com, Pragnesh Patel , Lukasz Majewski , Anup Patel , Simon Glass , Anatolij Gustschin Subject: [PATCH v12 10/18] clk: sifive: fu540-prci: Add ddr clock initialization Date: Mon, 25 May 2020 13:03:23 +0530 Message-Id: <20200525073333.14131-11-pragnesh.patel@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200525073333.14131-1-pragnesh.patel@sifive.com> References: <20200525073333.14131-1-pragnesh.patel@sifive.com> X-ClientProxiedBy: LNXP265CA0043.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:5c::31) To MN2PR13MB2797.namprd13.prod.outlook.com (2603:10b6:208:f2::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sachinj2-OptiPlex-7010.open-silicon.com (114.143.65.226) by LNXP265CA0043.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:5c::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.23 via Frontend Transport; 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u8 cfg0_offs; u8 cfg1_offs; + void (*release_reset)(struct __prci_data *pd); }; struct __prci_clock; @@ -477,6 +485,9 @@ static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable) if (enable) { __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK); + + if (pwd->release_reset) + pwd->release_reset(pd); } else { u32 r; @@ -496,11 +507,6 @@ static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = { .enable_clk = sifive_fu540_prci_clock_enable, }; -static const struct __prci_clock_ops sifive_fu540_prci_wrpll_ro_clk_ops = { - .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate, - .enable_clk = sifive_fu540_prci_clock_enable, -}; - /* TLCLKSEL clock integration */ static unsigned long sifive_fu540_prci_tlclksel_recalc_rate( @@ -522,6 +528,38 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate, }; +/** + * __prci_ddr_release_reset() - Release DDR reset + * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg + * + */ +static void __prci_ddr_release_reset(struct __prci_data *pd) +{ + u32 v; + + v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET); + v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK; + __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd); + + /* HACK to get the '1 full controller clock cycle'. */ + asm volatile ("fence"); + v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET); + v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK | + PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK | + PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK); + __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd); + + /* HACK to get the '1 full controller clock cycle'. */ + asm volatile ("fence"); + + /* + * These take like 16 cycles to actually propagate. We can't go sending + * stuff before they come out of reset. So wait. + */ + for (int i = 0; i < 256; i++) + asm volatile ("nop"); +} + /* * PRCI integration data for each WRPLL instance */ @@ -536,6 +574,7 @@ static struct __prci_wrpll_data __prci_corepll_data = { static struct __prci_wrpll_data __prci_ddrpll_data = { .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, + .release_reset = __prci_ddr_release_reset, }; static struct __prci_wrpll_data __prci_gemgxlpll_data = { @@ -557,7 +596,7 @@ static struct __prci_clock __prci_init_clocks[] = { [PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", - .ops = &sifive_fu540_prci_wrpll_ro_clk_ops, + .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_ddrpll_data, }, [PRCI_CLK_GEMGXLPLL] = {