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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id i59sm1600393qtb.58.2020.05.19.23.41.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2020 23:41:31 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Rick Chen , Bin Meng , Sean Anderson , Rick Chen , Lukas Auer Subject: [PATCH v11 13/21] riscv: Clear pending interrupts before enabling IPIs Date: Wed, 20 May 2020 02:41:03 -0400 Message-Id: <20200520064111.317605-14-seanga2@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200520064111.317605-1-seanga2@gmail.com> References: <20200520064111.317605-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean On some platforms (k210), the previous stage bootloader may have not cleared pending IPIs before transferring control to U-Boot. This can cause race conditions, as multiple harts all attempt to initialize the IPI controller at once. This patch clears IPIs before enabling them, ensuring that only one hart modifies shared memory at once. Signed-off-by: Sean Anderson Reviewed-by: Rick Chen --- Changes in v7: - Split of into its own patch arch/riscv/cpu/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 5f1c220e0c..f408e41ab9 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -65,6 +65,8 @@ _start: #else li t0, SIE_SSIE #endif + /* Clear any pending IPIs */ + csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif