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Tue, 19 May 2020 07:04:19 +0000 From: Pragnesh Patel To: u-boot@lists.denx.de Cc: atish.patra@wdc.com, palmerdabbelt@google.com, bmeng.cn@gmail.com, paul.walmsley@sifive.com, jagan@amarulasolutions.com, anup.patel@wdc.com, sagar.kadam@sifive.com, rick@andestech.com, Pragnesh Patel , Palmer Dabbelt Subject: [PATCH v11 02/18] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Date: Tue, 19 May 2020 12:33:27 +0530 Message-Id: <20200519070346.24479-3-pragnesh.patel@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200519070346.24479-1-pragnesh.patel@sifive.com> References: <20200519070346.24479-1-pragnesh.patel@sifive.com> X-ClientProxiedBy: LNXP265CA0025.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:5c::13) To MN2PR13MB2797.namprd13.prod.outlook.com (2603:10b6:208:f2::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sachinj2-OptiPlex-7010.open-silicon.com (114.143.65.226) by LNXP265CA0025.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:5c::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3000.20 via Frontend Transport; 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Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Jagan Teki Tested-by: Jagan Teki --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 14 +++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 2 + board/sifive/fu540/Kconfig | 2 + board/sifive/fu540/fu540.c | 111 ++++++------------ 4 files changed, 57 insertions(+), 72 deletions(-) create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi new file mode 100644 index 0000000000..db55773bd2 --- /dev/null +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) Copyright 2019 SiFive, Inc + */ + +/ { + soc { + otp: otp@10070000 { + compatible = "sifive,fu540-c000-otp"; + reg = <0x0 0x10070000 0x0 0x0FFF>; + fuse-count = <0x1000>; + }; + }; +}; diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 2aebfab646..9af089ffe7 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2019 Jagan Teki */ +#include "fu540-c000-u-boot.dtsi" + / { aliases { spi0 = &qspi0; diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 75661f35f8..4330ac4491 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -51,5 +51,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SIFIVE_GPIO imply CMD_GPIO imply SMP + imply MISC + imply SIFIVE_OTP endif diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c index 47a2090251..540638c919 100644 --- a/board/sifive/fu540/fu540.c +++ b/board/sifive/fu540/fu540.c @@ -10,94 +10,61 @@ #include #include #include +#include + +/* + * This define is a value used for error/unknown serial. + * If we really care about distinguishing errors and 0 is + * valid, we'll need a different one. + */ +#define ERROR_READING_SERIAL_NUMBER 0 #ifdef CONFIG_MISC_INIT_R -#define FU540_OTP_BASE_ADDR 0x10070000 - -struct fu540_otp_regs { - u32 pa; /* Address input */ - u32 paio; /* Program address input */ - u32 pas; /* Program redundancy cell selection input */ - u32 pce; /* OTP Macro enable input */ - u32 pclk; /* Clock input */ - u32 pdin; /* Write data input */ - u32 pdout; /* Read data output */ - u32 pdstb; /* Deep standby mode enable input (active low) */ - u32 pprog; /* Program mode enable input */ - u32 ptc; /* Test column enable input */ - u32 ptm; /* Test mode enable input */ - u32 ptm_rep;/* Repair function test mode enable input */ - u32 ptr; /* Test row enable input */ - u32 ptrim; /* Repair function enable input */ - u32 pwe; /* Write enable input (defines program cycle) */ -} __packed; - -#define BYTES_PER_FUSE 4 -#define NUM_FUSES 0x1000 - -static int fu540_otp_read(int offset, void *buf, int size) +#if CONFIG_IS_ENABLED(SIFIVE_OTP) +static u32 otp_read_serialnum(struct udevice *dev) { - struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR; - unsigned int i; - int fuseidx = offset / BYTES_PER_FUSE; - int fusecount = size / BYTES_PER_FUSE; - u32 fusebuf[fusecount]; - - /* check bounds */ - if (offset < 0 || size < 0) - return -EINVAL; - if (fuseidx >= NUM_FUSES) - return -EINVAL; - if ((fuseidx + fusecount) > NUM_FUSES) - return -EINVAL; + int ret; + u32 serial[2] = {0}; - /* init OTP */ - writel(0x01, ®s->pdstb); /* wake up from stand-by */ - writel(0x01, ®s->ptrim); /* enable repair function */ - writel(0x01, ®s->pce); /* enable input */ - - /* read all requested fuses */ - for (i = 0; i < fusecount; i++, fuseidx++) { - writel(fuseidx, ®s->pa); - - /* cycle clock to read */ - writel(0x01, ®s->pclk); - mdelay(1); - writel(0x00, ®s->pclk); - mdelay(1); - - /* read the value */ - fusebuf[i] = readl(®s->pdout); - } + for (int i = 0xfe * 4; i > 0; i -= 8) { + ret = misc_read(dev, i, serial, sizeof(serial)); - /* shut down */ - writel(0, ®s->pce); - writel(0, ®s->ptrim); - writel(0, ®s->pdstb); + if (ret != sizeof(serial)) { + printf("%s: error reading serial from OTP\n", __func__); + break; + } - /* copy out */ - memcpy(buf, fusebuf, size); + if (serial[0] == ~serial[1]) + return serial[0]; + } - return 0; + return ERROR_READING_SERIAL_NUMBER; } +#endif static u32 fu540_read_serialnum(void) { + u32 serial = ERROR_READING_SERIAL_NUMBER; + +#if CONFIG_IS_ENABLED(SIFIVE_OTP) + struct udevice *dev; int ret; - u32 serial[2] = {0}; - for (int i = 0xfe * 4; i > 0; i -= 8) { - ret = fu540_otp_read(i, serial, sizeof(serial)); - if (ret) { - printf("%s: error reading from OTP\n", __func__); - break; - } - if (serial[0] == ~serial[1]) - return serial[0]; + /* init OTP */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(sifive_otp), &dev); + + if (ret) { + debug("%s: could not find otp device\n", __func__); + return serial; } - return 0; + /* read serial from OTP and set env var */ + serial = otp_read_serialnum(dev); +#endif + + return serial; } static void fu540_setup_macaddr(u32 serialnum)