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Tue, 12 May 2020 18:47:46 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v3 3/9] pci: Move some PCIe register offset definitions to a common header Date: Tue, 12 May 2020 20:47:10 +0200 Message-Id: <20200512184716.2869-4-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDKsWRmVeSWpSXmKPExsWy7djPc7oh73fFGTw6rm2xccZ6VoupPfEW e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGVM nqNYMF2y4vHC/4wNjM9Euhg5OSQETCSm/ZvDDmILCaxglOjZH9DFyAVkf2GUeLzoMzuE85lR ou/UDXaYjlM9R1khEssZJQ4+P8UK0Q7Usmy+B4jNJmAo0Xu0jxHEFhEIkLj2cxojSAOzwFFG iTX7/7CAJIQFYiTO77/MBGKzCKhKTL1xBKyBV8BKYs3S12wQ2+QlVm84wAxicwpYS1zffIwZ ZJCEwDJ2iVW7F0Kd5CKx79h1RghbWOLV8S1QcRmJ/zvnM0E0NAM9t/s2O4QzgVHi/vEFUB3W EnfO/QJaxwF0n6bE+l36EGFHiemPdoCFJQT4JG68FQQJMwOZk7ZNZ4YI80p0tAlBVKtI/F41 nQnClpLofvKfBaLEQ2L5NAdIYPUB/d76iW0Co/wshF0LGBlXMYqnlhbnpqcWG+WllusVJ+YW l+al6yXn525iBKaZ0/+Of9nBuOtP0iFGAQ5GJR5ehtpdcUKsiWXFlbmHGCU4mJVEeFsyd8YJ 8aYkVlalFuXHF5XmpBYfYpTmYFES5zVe9DJWSCA9sSQ1OzW1ILUIJsvEwSnVwLh1z5TeG0az +Xfd3FB0+/pjvrtznq13cFFY6DvDfpdPqclmFr4pB1beCCs7lOQ78cOhHwlnVjI6zEmc2Ozz UzA48qrRrx/LPvqqt87Nqaz10/n2edvVDtvtE8Xe3rXad+vYkdXTZH6FOV5copT6IaCd1+u9 COurmnJJL6c5pbV9++z8vrjw1O5UYinOSDTUYi4qTgQAvI6vdC8DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsVy+t/xu7rB73fFGTxpUbXYOGM9q8XUnniL vW/62Sxu/GpjtVh75C67xZu2RkaLBZOfsFpsm7WczeLwm3ZWi29btjFavN3bye7A7THr/lk2 j9kNF1k85s06weKxc9Zddo+zd3YwevRtWcXosX7LVRaPzaerAzii9GyK8ktLUhUy8otLbJWi DS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DImz1EsmC5Z8Xjhf8YGxmciXYyc HBICJhKneo6ydjFycQgJLGWUOL/kGnsXIwdQQkpifosSRI2wxJ9rXWwQNZ8YJe61LGACSbAJ GEr0Hu1jBLFFBEIkXhy9wgRSxCxwllFiUecHVpCEsECUxIvfjWBFLAKqElNvHAGzeQWsJNYs fc0GsUFeYvWGA8wgNqeAtcT1zcfAbCGgmj3f3rFNYORbwMiwilEktbQ4Nz232FCvODG3uDQv XS85P3cTIzDstx37uXkH46WNwYcYBTgYlXh4GWp3xQmxJpYVV+YeYpTgYFYS4W3J3BknxJuS WFmVWpQfX1Sak1p8iNEU6KiJzFKiyfnAmMwriTc0NTS3sDQ0NzY3NrNQEuftEDgYIySQnliS mp2aWpBaBNPHxMEp1cAo8NYxO8Jqj6PRV77edRqM6d/fPNh+ckp9/fKwsoWn/NSufp8boJey O+/Wy/nTzpj1bt4798PtHSdmhmywaQj0KVYtD5qat1b7GMvEYBcra0Ze5hft2f6SH/t0Lumf lXf9Pqv43uddiwVjUyRvrP5qZmy664CmlFb7nrstPeLfGxjWC3ooze9TYinOSDTUYi4qTgQA d2ZzFZECAAA= X-CMS-MailID: 20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5 X-Msg-Generator: CA X-RootMTR: 20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5 References: <20200512184716.2869-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki Reviewed-by: Bin Meng Reviewed-by: Nicolas Saenz Julienne --- Changes since v1: - none. Changes since RFC: - whitespace clean up. --- drivers/pci/pci-rcar-gen3.c | 8 -------- drivers/pci/pcie_intel_fpga.c | 3 --- include/pci.h | 13 +++++++++++-- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 30eff67..393f1c9 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -117,14 +117,6 @@ #define RCAR_PCI_MAX_RESOURCES 4 #define MAX_NR_INBOUND_MAPS 6 -#define PCI_EXP_FLAGS 2 /* Capabilities register */ -#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - enum { RCAR_PCI_ACCESS_READ, RCAR_PCI_ACCESS_WRITE, diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 6a9f29c..69363a0 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -65,9 +65,6 @@ #define IS_ROOT_PORT(pcie, bdf) \ ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) -#define PCI_EXP_LNKSTA 18 /* Link Status */ -#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ - /** * struct intel_fpga_pcie - Intel FPGA PCIe controller state * @bus: Pointer to the PCI bus diff --git a/include/pci.h b/include/pci.h index aff56b2..dfdbb32 100644 --- a/include/pci.h +++ b/include/pci.h @@ -471,10 +471,19 @@ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ /* PCI Express capabilities */ +#define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ -#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ -#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +#define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ /* Include the ID list */