@@ -36,6 +36,7 @@ config BCM2711_32B
select BCM2711
select ARMV7_LPAE
select CPU_V7A
+ select PHYS_64BIT
config BCM2711_64B
bool "Broadcom BCM2711 SoC 64-bit support"
@@ -8,4 +8,10 @@
extern unsigned long rpi_bcm283x_base;
+#ifdef CONFIG_ARMV7_LPAE
+#include <addr_map.h>
+#define phys_to_virt addrmap_phys_to_virt
+#define virt_to_phys addrmap_virt_to_phys
+#endif
+
#endif
@@ -145,6 +145,20 @@ int mach_cpu_init(void)
}
#ifdef CONFIG_ARMV7_LPAE
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
+#include <addr_map.h>
+
+void init_addr_map(void)
+{
+ mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+ DCACHE_OFF);
+ addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 0);
+}
+
void enable_caches(void)
{
dcache_enable();
@@ -63,6 +63,11 @@
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#endif
+#ifdef CONFIG_ARMV7_LPAE
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 2
+#endif
+
/* Devices */
/* GPIO */
#define CONFIG_BCM2835_GPIO
Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> --- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/include/mach/base.h | 6 ++++++ arch/arm/mach-bcm283x/init.c | 14 ++++++++++++++ include/configs/rpi.h | 5 +++++ 4 files changed, 26 insertions(+)