diff mbox series

[v1,08/10] sysreset: Add Octeon sysreset driver

Message ID 20200502085944.13444-9-sr@denx.de
State Superseded
Delegated to: Daniel Schwierzeck
Headers show
Series mips: Add initial Octeon MIPS64 base support | expand

Commit Message

Stefan Roese May 2, 2020, 8:59 a.m. UTC 
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.

Signed-off-by: Stefan Roese <sr@denx.de>
---

 drivers/sysreset/Kconfig           |  7 ++++
 drivers/sysreset/Makefile          |  1 +
 drivers/sysreset/sysreset_octeon.c | 52 ++++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_octeon.c

Comments

Daniel Schwierzeck May 13, 2020, 3:03 p.m. UTC | #1 
Am 02.05.20 um 10:59 schrieb Stefan Roese:
> This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
> family.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> ---
> 
>  drivers/sysreset/Kconfig           |  7 ++++
>  drivers/sysreset/Makefile          |  1 +
>  drivers/sysreset/sysreset_octeon.c | 52 ++++++++++++++++++++++++++++++
>  3 files changed, 60 insertions(+)
>  create mode 100644 drivers/sysreset/sysreset_octeon.c
> 
> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
> index 4be7433404..6ebc90e1d3 100644
> --- a/drivers/sysreset/Kconfig
> +++ b/drivers/sysreset/Kconfig
> @@ -57,6 +57,13 @@ config SYSRESET_MICROBLAZE
>  	help
>  	  This is soft reset on Microblaze which does jump to 0x0 address.
>  
> +config SYSRESET_OCTEON
> +	bool "Enable support for Marvell Octeon SoC family"
> +	depends on ARCH_OCTEON
> +	help
> +	  This enables the system reset driver support for Marvell Octeon
> +	  SoCs.
> +
>  config SYSRESET_PSCI
>  	bool "Enable support for PSCI System Reset"
>  	depends on ARM_PSCI_FW
> diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
> index 3ed4bab9e3..df2293b848 100644
> --- a/drivers/sysreset/Makefile
> +++ b/drivers/sysreset/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
>  obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
>  obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
>  obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
> +obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
>  obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
>  obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
>  obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
> diff --git a/drivers/sysreset/sysreset_octeon.c b/drivers/sysreset/sysreset_octeon.c
> new file mode 100644
> index 0000000000..a05dac3226
> --- /dev/null
> +++ b/drivers/sysreset/sysreset_octeon.c
> @@ -0,0 +1,52 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Stefan Roese <sr@denx.de>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <sysreset.h>
> +#include <asm/io.h>
> +
> +#define RST_SOFT_RST		0x0080
> +
> +struct octeon_sysreset_data {
> +	void __iomem *base;
> +};
> +
> +static int octeon_sysreset_request(struct udevice *dev, enum sysreset_t type)
> +{
> +	struct octeon_sysreset_data *data = dev_get_priv(dev);
> +
> +	writeq(1, data->base + RST_SOFT_RST);
> +
> +	return -EINPROGRESS;
> +}
> +
> +static int octeon_sysreset_probe(struct udevice *dev)
> +{
> +	struct octeon_sysreset_data *data = dev_get_priv(dev);
> +
> +	data->base = dev_remap_addr(dev);
> +
> +	return 0;
> +}
> +
> +static struct sysreset_ops octeon_sysreset = {
> +	.request = octeon_sysreset_request,
> +};
> +
> +static const struct udevice_id octeon_sysreset_ids[] = {
> +	{ .compatible = "mrvl,cn7xxx-rst" },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(sysreset_octeon) = {
> +	.id	= UCLASS_SYSRESET,
> +	.name	= "octeon_sysreset",
> +	.priv_auto_alloc_size = sizeof(struct octeon_sysreset_data),
> +	.ops	= &octeon_sysreset,
> +	.probe	= octeon_sysreset_probe,
> +	.of_match = octeon_sysreset_ids,
> +};
> 

have you planned to add a real reset driver? If you add syscon/regmap
support to that reset driver, then you could simply use the generic
sysreset_syscon.c driver.
Stefan Roese May 14, 2020, 8:55 a.m. UTC | #2 
On 13.05.20 17:03, Daniel Schwierzeck wrote:
> 
> 
> Am 02.05.20 um 10:59 schrieb Stefan Roese:
>> This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
>> family.
>>
>> Signed-off-by: Stefan Roese <sr@denx.de>
>> ---
>>
>>   drivers/sysreset/Kconfig           |  7 ++++
>>   drivers/sysreset/Makefile          |  1 +
>>   drivers/sysreset/sysreset_octeon.c | 52 ++++++++++++++++++++++++++++++
>>   3 files changed, 60 insertions(+)
>>   create mode 100644 drivers/sysreset/sysreset_octeon.c
>>
>> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
>> index 4be7433404..6ebc90e1d3 100644
>> --- a/drivers/sysreset/Kconfig
>> +++ b/drivers/sysreset/Kconfig
>> @@ -57,6 +57,13 @@ config SYSRESET_MICROBLAZE
>>   	help
>>   	  This is soft reset on Microblaze which does jump to 0x0 address.
>>   
>> +config SYSRESET_OCTEON
>> +	bool "Enable support for Marvell Octeon SoC family"
>> +	depends on ARCH_OCTEON
>> +	help
>> +	  This enables the system reset driver support for Marvell Octeon
>> +	  SoCs.
>> +
>>   config SYSRESET_PSCI
>>   	bool "Enable support for PSCI System Reset"
>>   	depends on ARM_PSCI_FW
>> diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
>> index 3ed4bab9e3..df2293b848 100644
>> --- a/drivers/sysreset/Makefile
>> +++ b/drivers/sysreset/Makefile
>> @@ -10,6 +10,7 @@ obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
>>   obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
>>   obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
>>   obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
>> +obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
>>   obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
>>   obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
>>   obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
>> diff --git a/drivers/sysreset/sysreset_octeon.c b/drivers/sysreset/sysreset_octeon.c
>> new file mode 100644
>> index 0000000000..a05dac3226
>> --- /dev/null
>> +++ b/drivers/sysreset/sysreset_octeon.c
>> @@ -0,0 +1,52 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2020 Stefan Roese <sr@denx.de>
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <errno.h>
>> +#include <sysreset.h>
>> +#include <asm/io.h>
>> +
>> +#define RST_SOFT_RST		0x0080
>> +
>> +struct octeon_sysreset_data {
>> +	void __iomem *base;
>> +};
>> +
>> +static int octeon_sysreset_request(struct udevice *dev, enum sysreset_t type)
>> +{
>> +	struct octeon_sysreset_data *data = dev_get_priv(dev);
>> +
>> +	writeq(1, data->base + RST_SOFT_RST);
>> +
>> +	return -EINPROGRESS;
>> +}
>> +
>> +static int octeon_sysreset_probe(struct udevice *dev)
>> +{
>> +	struct octeon_sysreset_data *data = dev_get_priv(dev);
>> +
>> +	data->base = dev_remap_addr(dev);
>> +
>> +	return 0;
>> +}
>> +
>> +static struct sysreset_ops octeon_sysreset = {
>> +	.request = octeon_sysreset_request,
>> +};
>> +
>> +static const struct udevice_id octeon_sysreset_ids[] = {
>> +	{ .compatible = "mrvl,cn7xxx-rst" },
>> +	{ }
>> +};
>> +
>> +U_BOOT_DRIVER(sysreset_octeon) = {
>> +	.id	= UCLASS_SYSRESET,
>> +	.name	= "octeon_sysreset",
>> +	.priv_auto_alloc_size = sizeof(struct octeon_sysreset_data),
>> +	.ops	= &octeon_sysreset,
>> +	.probe	= octeon_sysreset_probe,
>> +	.of_match = octeon_sysreset_ids,
>> +};
>>
> 
> have you planned to add a real reset driver? If you add syscon/regmap
> support to that reset driver, then you could simply use the generic
> sysreset_syscon.c driver.

With a "real reset driver" you are referring to a driver capable of
resetting multiple (all) SoC internal peripherals?

If yes, I thought about adding such a driver. But AFAICT, Octeon does
not support resetting its peripherals via some grouped registers. The
SoC itself can be reset via RST_SOFT_RST register but not its
peripherals.

Thanks,
Stefan
diff mbox series

Patch

diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 4be7433404..6ebc90e1d3 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -57,6 +57,13 @@  config SYSRESET_MICROBLAZE
 	help
 	  This is soft reset on Microblaze which does jump to 0x0 address.
 
+config SYSRESET_OCTEON
+	bool "Enable support for Marvell Octeon SoC family"
+	depends on ARCH_OCTEON
+	help
+	  This enables the system reset driver support for Marvell Octeon
+	  SoCs.
+
 config SYSRESET_PSCI
 	bool "Enable support for PSCI System Reset"
 	depends on ARM_PSCI_FW
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 3ed4bab9e3..df2293b848 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -10,6 +10,7 @@  obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
 obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
 obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
+obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
 obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
 obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
 obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
diff --git a/drivers/sysreset/sysreset_octeon.c b/drivers/sysreset/sysreset_octeon.c
new file mode 100644
index 0000000000..a05dac3226
--- /dev/null
+++ b/drivers/sysreset/sysreset_octeon.c
@@ -0,0 +1,52 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+
+#define RST_SOFT_RST		0x0080
+
+struct octeon_sysreset_data {
+	void __iomem *base;
+};
+
+static int octeon_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct octeon_sysreset_data *data = dev_get_priv(dev);
+
+	writeq(1, data->base + RST_SOFT_RST);
+
+	return -EINPROGRESS;
+}
+
+static int octeon_sysreset_probe(struct udevice *dev)
+{
+	struct octeon_sysreset_data *data = dev_get_priv(dev);
+
+	data->base = dev_remap_addr(dev);
+
+	return 0;
+}
+
+static struct sysreset_ops octeon_sysreset = {
+	.request = octeon_sysreset_request,
+};
+
+static const struct udevice_id octeon_sysreset_ids[] = {
+	{ .compatible = "mrvl,cn7xxx-rst" },
+	{ }
+};
+
+U_BOOT_DRIVER(sysreset_octeon) = {
+	.id	= UCLASS_SYSRESET,
+	.name	= "octeon_sysreset",
+	.priv_auto_alloc_size = sizeof(struct octeon_sysreset_data),
+	.ops	= &octeon_sysreset,
+	.probe	= octeon_sysreset_probe,
+	.of_match = octeon_sysreset_ids,
+};