diff mbox series

ARM: dts: stm32: Synchronize DDR setttings on DH SoMs

Message ID 20200429130838.16891-1-marex@denx.de
State Accepted
Commit 92ca0f7446c5948f364bfb3377f9e08fad7ff857
Delegated to: Patrick Delaunay
Headers show
Series ARM: dts: stm32: Synchronize DDR setttings on DH SoMs | expand

Commit Message

Marek Vasut April 29, 2020, 1:08 p.m. UTC 
Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put them
into use by the board file instead of the default ones. These new DRAM
settings are a better fit for the SoMs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
---
Note that these settings are generated by the cubemx tool
---
 .../stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi | 120 ++++++++++++++++++
 .../stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi | 120 ++++++++++++++++++
 .../stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 120 ++++++++++++++++++
 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi    |   5 +-
 arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi    |   5 +-
 board/dhelectronics/dh_stm32mp1/board.c       |   8 +-
 6 files changed, 372 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi
 create mode 100644 arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi
 create mode 100644 arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi

Comments

Marek Vasut May 12, 2020, 4:57 p.m. UTC | #1 
On 4/29/20 3:08 PM, Marek Vasut wrote:
> Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put them
> into use by the board file instead of the default ones. These new DRAM
> settings are a better fit for the SoMs.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> Note that these settings are generated by the cubemx tool

Seems like quite a few of those stm32mp1 patches still aren't in
u-boot/master ?
Patrick DELAUNAY May 13, 2020, 9:27 a.m. UTC | #2 
Dear Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: mercredi 29 avril 2020 15:09
> 
> Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put
> them into use by the board file instead of the default ones. These new DRAM
> settings are a better fit for the SoMs.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> Note that these settings are generated by the cubemx tool
> ---
>  .../stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi | 120 ++++++++++++++++++
> .../stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi | 120 ++++++++++++++++++
> .../stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 120 ++++++++++++++++++
>  arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi    |   5 +-
>  arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi    |   5 +-
>  board/dhelectronics/dh_stm32mp1/board.c       |   8 +-
>  6 files changed, 372 insertions(+), 6 deletions(-)  create mode 100644
> arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi
>  create mode 100644 arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi
>  create mode 100644 arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi
> 

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

Thanks

Patrick
Patrick DELAUNAY May 13, 2020, 12:26 p.m. UTC | #3 
Hi Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: mardi 12 mai 2020 18:58
> 
> On 4/29/20 3:08 PM, Marek Vasut wrote:
> > Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put
> them
> > into use by the board file instead of the default ones. These new DRAM
> > settings are a better fit for the SoMs.
> >
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Patrick Delaunay <patrick.delaunay@st.com>
> > Cc: Patrice Chotard <patrice.chotard@st.com>
> > ---
> > Note that these settings are generated by the cubemx tool
> 
> Seems like quite a few of those stm32mp1 patches still aren't in u-boot/master ?

Yes,

I am preparing a pull request for this week or beginning of next week...

This patch will  be part of it.

Regards

Patrick
Marek Vasut May 13, 2020, 12:33 p.m. UTC | #4 
On 5/13/20 2:26 PM, Patrick DELAUNAY wrote:
> Hi Marek,
> 
>> From: Marek Vasut <marex@denx.de>
>> Sent: mardi 12 mai 2020 18:58
>>
>> On 4/29/20 3:08 PM, Marek Vasut wrote:
>>> Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put
>> them
>>> into use by the board file instead of the default ones. These new DRAM
>>> settings are a better fit for the SoMs.
>>>
>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>> Cc: Patrick Delaunay <patrick.delaunay@st.com>
>>> Cc: Patrice Chotard <patrice.chotard@st.com>
>>> ---
>>> Note that these settings are generated by the cubemx tool
>>
>> Seems like quite a few of those stm32mp1 patches still aren't in u-boot/master ?
> 
> Yes,
> 
> I am preparing a pull request for this week or beginning of next week...
> 
> This patch will  be part of it.

Great, thanks.
Patrick DELAUNAY May 14, 2020, 9:35 a.m. UTC | #5 
Hi Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: mercredi 29 avril 2020 15:09
> 
> Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put
> them into use by the board file instead of the default ones. These new DRAM
> settings are a better fit for the SoMs.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> Note that these settings are generated by the cubemx tool
> ---
>  .../stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi | 120 ++++++++++++++++++
> .../stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi | 120 ++++++++++++++++++
> .../stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 120 ++++++++++++++++++
>  arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi    |   5 +-
>  arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi    |   5 +-
>  board/dhelectronics/dh_stm32mp1/board.c       |   8 +-
>  6 files changed, 372 insertions(+), 6 deletions(-)  create mode 100644
> arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi
>  create mode 100644 arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi
>  create mode 100644 arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi
> 

Applied to u-boot-stm/master, thanks!

Regards

Patrick
diff mbox series

Patch

diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi
new file mode 100644
index 0000000000..b3eb280f96
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi
@@ -0,0 +1,120 @@ 
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020, DH electronics - All Rights Reserved
+ *
+ * STM32MP15xx DHSOM configuration
+ * 2x DDR3L 1Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
+ * Reference used W631GU6MB15I from Winbond
+ *
+ * DDR type / Platform	DDR3/3L
+ * freq		533MHz
+ * width	32
+ * datasheet	0  = W631GU6MB15I / DDR3-1333
+ * DDR density	2
+ * timing mode	optimized
+ * address mapping : RBC
+ * Tc > + 85C : J
+ */
+#define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz
+#define DDR_MEM_NAME "DDR3L 32bits 2x1Gb 533MHz"
+#define DDR_MEM_SPEED 533000
+#define DDR_MEM_SIZE 0x10000000
+
+#define DDR_MSTR 0x00040401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0040008B
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B1214
+#define DDR_DRAMTMG1 0x000A041C
+#define DDR_DRAMTMG2 0x0608090F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x08040608
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02060105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00000C01
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100C03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100C03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_ADDRMAP1 0x00080808
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x07070707
+#define DDR_ADDRMAP6 0x0F0F0F07
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022AA5B
+#define DDR_PTR1 0x04841104
+#define DDR_PTR2 0x042DA068
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200011F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x38D488D0
+#define DDR_DTPR1 0x098B00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000840
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000248
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x00000038
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
+
+#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi
new file mode 100644
index 0000000000..ed3a5248f8
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi
@@ -0,0 +1,120 @@ 
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020, DH electronics - All Rights Reserved
+ *
+ * STM32MP15xx DHSOM configuration
+ * 2x DDR3L 2Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
+ * Reference used W632GU6NB15I from Winbond
+ *
+ * DDR type / Platform	DDR3/3L
+ * freq		533MHz
+ * width	32
+ * datasheet	0  = W632GU6NB15I / DDR3-1333
+ * DDR density	4
+ * timing mode	optimized
+ * address mapping : RBC
+ * Tc > + 85C : J
+ */
+#define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz
+#define DDR_MEM_NAME "DDR3L 32bits 2x2Gb 533MHz"
+#define DDR_MEM_SPEED 533000
+#define DDR_MEM_SIZE 0x20000000
+
+#define DDR_MSTR 0x00040401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0040008B
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B1214
+#define DDR_DRAMTMG1 0x000A041C
+#define DDR_DRAMTMG2 0x0608090F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x08040608
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02060105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00000C01
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100C03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100C03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_ADDRMAP1 0x00080808
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x07070707
+#define DDR_ADDRMAP6 0x0F0F0707
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022AA5B
+#define DDR_PTR1 0x04841104
+#define DDR_PTR2 0x042DA068
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200011F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x38D488D0
+#define DDR_DTPR1 0x098B00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000840
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000248
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x00000038
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
+
+#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi
new file mode 100644
index 0000000000..d5813d64b0
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi
@@ -0,0 +1,120 @@ 
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020, DH electronics - All Rights Reserved
+ *
+ * STM32MP15xx DHSOM configuration
+ * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
+ * Reference used W634GU6NB15I from Winbond
+ *
+ * DDR type / Platform	DDR3/3L
+ * freq		533MHz
+ * width	32
+ * datasheet	0  = W634GU6NB15I / DDR3-1333
+ * DDR density	8
+ * timing mode	optimized
+ * address mapping : RBC
+ * Tc > + 85C : J
+ */
+#define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz
+#define DDR_MEM_NAME "DDR3L 32bits 2x4Gb 533MHz"
+#define DDR_MEM_SPEED 533000
+#define DDR_MEM_SIZE 0x40000000
+
+#define DDR_MSTR 0x00040401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0040008B
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B1214
+#define DDR_DRAMTMG1 0x000A041C
+#define DDR_DRAMTMG2 0x0608090F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x08040608
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02060105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00000C01
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100C03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100C03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_ADDRMAP1 0x00080808
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x07070707
+#define DDR_ADDRMAP6 0x0F070707
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022AA5B
+#define DDR_PTR1 0x04841104
+#define DDR_PTR2 0x042DA068
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200011F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x38D488D0
+#define DDR_DTPR1 0x098B00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000840
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000248
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x00000038
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
+
+#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index aee9ee5844..75d75266e8 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -5,8 +5,9 @@ 
 
 #include <dt-bindings/clock/stm32mp1-clksrc.h>
 #include "stm32mp15-u-boot.dtsi"
-#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
-#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
+#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
+#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
+#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 17aa2bfc85..bd4c2adc35 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -9,8 +9,9 @@ 
 
 #include <dt-bindings/clock/stm32mp1-clksrc.h>
 #include "stm32mp15-u-boot.dtsi"
-#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
-#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
+#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
+#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
+#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
 
 / {
 	u-boot,dm-pre-reloc;
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 9a2926bbe5..80baebb0b1 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -179,12 +179,16 @@  static void board_get_coding_straps(void)
 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
 					 const char *name)
 {
+	if (ddr3code == 1 &&
+	    !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
+		return 0;
+
 	if (ddr3code == 2 &&
-	    !strcmp(name, "st,ddr3-1066-888-bin-g-1x4gb-533mhz"))
+	    !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
 		return 0;
 
 	if (ddr3code == 3 &&
-	    !strcmp(name, "st,ddr3-1066-888-bin-g-2x4gb-533mhz"))
+	    !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
 		return 0;
 
 	return -EINVAL;