From patchwork Mon Apr 20 08:46:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1273211 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 495L0t1636z9sR4 for ; Mon, 20 Apr 2020 18:47:10 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8A79181C62; Mon, 20 Apr 2020 10:46:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7A02581C71; Mon, 20 Apr 2020 10:46:41 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 023E081737 for ; Mon, 20 Apr 2020 10:46:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ley.foon.tan@intel.com IronPort-SDR: 8X619R2U+F+YmXytzv5PPjObuZ+eaFXaUSYlJwIKxKEx+Ghm8yzGxOX4PiH+ywrMEYTKEKXero 3TTC9UqSKYWg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Apr 2020 01:46:36 -0700 IronPort-SDR: X78qKovhI3VdlKJhMsW5ErlhPkt7yWBijAQNoCcqyvlvZjN54gM5h5LLPSDoqIaZ20k/6YtCh3 WnbAhBWNdIlA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,406,1580803200"; d="scan'208";a="273115922" Received: from ppglcf0015.png.intel.com ([10.226.229.35]) by orsmga002.jf.intel.com with ESMTP; 20 Apr 2020 01:46:33 -0700 From: Ley Foon Tan To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Chin Liang See , Simon Goldschmidt , Tien Fong Chee , Ley Foon Tan Subject: [PATCH v2 3/7] ddr: altera: arria10: Change to use reset DM function Date: Mon, 20 Apr 2020 16:46:20 +0800 Message-Id: <20200420084624.110026-4-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20200420084624.110026-1-ley.foon.tan@intel.com> References: <20200420084624.110026-1-ley.foon.tan@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Change to use reset DM function and remove unused socfpga_reset_deassert_noc_ddr_scheduler(). Signed-off-by: Ley Foon Tan --- v2: - Call to reset_assert_bulk() if failed in _probe(). --- .../include/mach/reset_manager_arria10.h | 1 - arch/arm/mach-socfpga/reset_manager_arria10.c | 7 ----- drivers/ddr/altera/sdram_arria10.c | 26 ++++++++++--------- 3 files changed, 14 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 22e4eb33de88..a0fad7c1e2fc 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -9,7 +9,6 @@ #include void socfpga_watchdog_disable(void); -void socfpga_reset_deassert_noc_ddr_scheduler(void); int socfpga_reset_deassert_bridges_handoff(void); void socfpga_reset_deassert_osc1wd0(void); int socfpga_bridges_reset(void); diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index aa5299415a74..edfe250ec0bc 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -62,13 +62,6 @@ void socfpga_watchdog_disable(void) ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); } -/* Release NOC ddr scheduler from reset */ -void socfpga_reset_deassert_noc_ddr_scheduler(void) -{ - clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST, - ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK); -} - static int get_bridge_init_val(const void *blob, int compat_id) { int node; diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 5d092f1f3b73..3374efaae801 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -10,19 +10,21 @@ #include #include #include +#include #include #include #include #include #include -#include #include +#include #include DECLARE_GLOBAL_DATA_PTR; struct altera_sdram_priv { struct ram_info info; + struct reset_ctl_bulk resets; }; struct altera_sdram_platdata { @@ -152,7 +154,7 @@ static int emif_reset(struct altera_sdram_platdata *plat) return 0; } -static int ddr_setup(struct altera_sdram_platdata *plat) +static int sdram_startup(struct altera_sdram_platdata *plat) { int i, ret; @@ -198,16 +200,6 @@ static void sdram_init_ecc_bits(u32 size) dcache_disable(); } -/* Function to startup the SDRAM*/ -static int sdram_startup(struct altera_sdram_platdata *plat) -{ - /* Release NOC ddr scheduler from reset */ - socfpga_reset_deassert_noc_ddr_scheduler(); - - /* Bringup the DDR (calibration and configuration) */ - return ddr_setup(plat); -} - static u64 sdram_size_calc(struct altera_sdram_platdata *plat) { u32 dramaddrw = readl(plat->iohmc + DRAMADDRW); @@ -703,8 +695,17 @@ static int altera_sdram_ofdata_to_platdata(struct udevice *dev) static int altera_sdram_probe(struct udevice *dev) { + int ret; struct altera_sdram_priv *priv = dev_get_priv(dev); + ret = reset_get_bulk(dev, &priv->resets); + if (ret) { + dev_err(dev, "Can't get reset: %d\n", ret); + return -ENODEV; + } + + reset_deassert_bulk(&priv->resets); + if (ddr_calibration_sequence(dev->platdata) != 0) { puts("SDRAM init failed.\n"); goto failed; @@ -716,6 +717,7 @@ static int altera_sdram_probe(struct udevice *dev) return 0; failed: + reset_assert_bulk(&priv->resets); return -ENODEV; }