diff mbox series

ARC: HSDK: CGU: fix tunnel clock calculation

Message ID 20200416193511.27185-1-Eugeniy.Paltsev@synopsys.com
State Accepted
Commit 7b50db8242b62c85a19da9521b703faa858f4a63
Delegated to: Alexey Brodkin
Headers show
Series ARC: HSDK: CGU: fix tunnel clock calculation | expand

Commit Message

Eugeniy Paltsev April 16, 2020, 7:35 p.m. UTC 
We set wrong tunnel PLL frequency when we request 125MHz tunnel clock.
Fix that.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
 drivers/clk/clk-hsdk-cgu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 4637b9fdf15..6eaafdeaf99 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -144,7 +144,7 @@  struct hsdk_tun_clk_cfg {
 
 static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
 	{ 25000000,  50000000,  75000000,  100000000, 125000000, 150000000 },
-	{ 600000000, 600000000, 600000000, 600000000, 700000000, 600000000 }, {
+	{ 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
 	{ CGU_TUN_IDIV_TUN,	{ 24,	12,	8,	6,	6,	4 } },
 	{ CGU_TUN_IDIV_ROM,	{ 4,	4,	4,	4,	5,	4 } },
 	{ CGU_TUN_IDIV_PWM,	{ 8,	8,	8,	8,	10,	8 } }
@@ -205,6 +205,7 @@  static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
 	{ 500000000,  0, 14, 1, 0 },
 	{ 600000000,  0, 17, 1, 0 },
 	{ 700000000,  0, 20, 1, 0 },
+	{ 750000000,  1, 44, 1, 0 },
 	{ 800000000,  0, 23, 1, 0 },
 	{ 900000000,  1, 26, 0, 0 },
 	{ 1000000000, 1, 29, 0, 0 },