diff mbox series

[4/4,RFC] ARM: stm32: Implement DDR3 coding on DHCOR SoM

Message ID 20200331234807.432637-4-marex@denx.de
State RFC
Delegated to: Patrick Delaunay
Headers show
Series [1/4,RFC] ARM: stm32: Implement board coding on AV96 | expand

Commit Message

Marek Vasut March 31, 2020, 11:48 p.m. UTC
The DHCOR board does exist in multiple variants with different DDR3
DRAM sizes. To cater for all of them, implement DDR3 code handling.
There are two GPIOs which code the DRAM size populated on the SoM,
read them out and use the value to pick the correct DDR3 config.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
---
 arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi |  2 ++
 board/dhelectronics/dh_stm32mp1/board.c    | 26 +++++++++++++++++++++-
 2 files changed, 27 insertions(+), 1 deletion(-)

Comments

Patrick Delaunay April 7, 2020, 1:12 p.m. UTC | #1
Dear Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: mercredi 1 avril 2020 01:48
> 
> The DHCOR board does exist in multiple variants with different DDR3 DRAM
> sizes. To cater for all of them, implement DDR3 code handling.
> There are two GPIOs which code the DRAM size populated on the SoM, read
> them out and use the value to pick the correct DDR3 config.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---

It is ok for me.

Only check the name check with remarks on previous patch of the serie.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

Thanks

Patrick
diff mbox series

Patch

diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 17a23ae21c..6db4ac37e1 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -9,6 +9,7 @@ 
 
 #include <dt-bindings/clock/stm32mp1-clksrc.h>
 #include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
 
 / {
@@ -16,6 +17,7 @@ 
 	config {
 		u-boot,dm-pre-reloc;
 		#gpio-cells = <2>;
+		dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
 		dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
 	};
 };
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 36b8652521..a081a3f86b 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -134,6 +134,7 @@  int checkboard(void)
 }
 
 #ifdef CONFIG_SPL_BUILD
+static u8 ddr3code __section("data");
 static u8 somcode __section("data");
 
 static void board_get_coding_straps(void)
@@ -149,6 +150,16 @@  static void board_get_coding_straps(void)
 	}
 
 	for (i = 0; i < 2; i++) {
+		ret = gpio_request_by_name_nodev(node, "dh,ddr3-coding-gpios",
+						 i, &gpio, GPIOD_IS_IN);
+		if (ret) {
+			printf("%s: could not find a /config/dh,ddr3-coding-gpios[%i]\n",
+			      __func__, i);
+			return;
+		}
+
+		ddr3code |= !!dm_gpio_get_value(&gpio) << i;
+
 		ret = gpio_request_by_name_nodev(node, "dh,som-coding-gpios",
 						 i, &gpio, GPIOD_IS_IN);
 		if (ret) {
@@ -160,7 +171,7 @@  static void board_get_coding_straps(void)
 		somcode |= !!dm_gpio_get_value(&gpio) << i;
 	}
 
-	printf("Code:  SoM:%x\n", somcode);
+	printf("Code:  DDR3:%x SoM:%x\n", ddr3code, somcode);
 }
 
 void board_init_f(ulong dummy)
@@ -206,6 +217,19 @@  void board_init_f(ulong dummy)
 	}
 }
 
+int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
+					 const char *name)
+{
+	if (ddr3code == 2 &&
+	    !strcmp(name, "config@ddr3-1066-888-bin-g-1x4gb-533mhz"))
+
+	if (ddr3code == 3 &&
+	    !strcmp(name, "config@ddr3-1066-888-bin-g-2x4gb-533mhz"))
+		return 0;
+
+	return -EINVAL;
+}
+
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {