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[v3,02/17] spi: spi-mem: allow specifying a command's extension

Message ID 20200330154550.21179-3-p.yadav@ti.com
State Changes Requested
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series mtd: spi-nor-core: add xSPI Octal DTR support | expand

Commit Message

Pratyush Yadav March 30, 2020, 3:45 p.m. UTC
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode. When it is "hex" an additional opcode byte based
is sent with the command whose value can be anything.

So, make opcode a 16-bit value and add a 'nbytes', similar to how
multiple address widths are handled.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
 include/spi-mem.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
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diff --git a/include/spi-mem.h b/include/spi-mem.h
index fc39d08c3c..c55b98fe3e 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -70,6 +70,8 @@  enum spi_mem_data_dir {
  * struct spi_mem_op - describes a SPI memory operation
+ * @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is
+ *		sent MSB-first.
  * @cmd.buswidth: number of IO lines used to transmit the command
  * @cmd.opcode: operation opcode
  * @cmd.dtr: whether the command opcode should be sent in DTR mode or not
@@ -93,9 +95,10 @@  enum spi_mem_data_dir {
 struct spi_mem_op {
 	struct {
+		u8 nbytes;
 		u8 buswidth;
-		u8 opcode;
 		u8 dtr : 1;
+		u16 opcode;
 	} cmd;
 	struct {