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[1/2] configs: socfpga: Add QSPI support for Cyclone 5

Message ID 20200221012506.5042-1-ley.foon.tan@intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series [1/2] configs: socfpga: Add QSPI support for Cyclone 5 | expand

Commit Message

Tan, Ley Foon Feb. 21, 2020, 1:25 a.m. UTC
Add QSPI boot support to boot target devices list.
Platform can provide their own boot settings through SOCFPGA_BOOT_SETTINGS
macro if needed.

Add SOCFPGA_BOOT_SETTINGS for Cyclone 5.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 include/configs/socfpga_common.h         | 18 ++++++++++++++++++
 include/configs/socfpga_cyclone5_socdk.h | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

Comments

Ley Foon Tan March 2, 2020, 9:34 a.m. UTC | #1
On Fri, Feb 21, 2020 at 9:25 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>
> Add QSPI boot support to boot target devices list.
> Platform can provide their own boot settings through SOCFPGA_BOOT_SETTINGS
> macro if needed.
>
> Add SOCFPGA_BOOT_SETTINGS for Cyclone 5.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  include/configs/socfpga_common.h         | 18 ++++++++++++++++++
>  include/configs/socfpga_cyclone5_socdk.h | 18 ++++++++++++++++++
>  2 files changed, 36 insertions(+)
>
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index 8d10469e7c..f3ddfca289 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -228,11 +228,28 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>  #define BOOT_TARGET_DEVICES_MMC(func)
>  #endif
>
> +#ifdef CONFIG_CMD_SF
> +#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
> +#else
> +#define BOOT_TARGET_DEVICES_QSPI(func)
> +#endif
> +
> +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
> +       "bootcmd_qspi=run qspiload; run qspiboot\0"
> +
> +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
> +       "qspi "
> +
>  #define BOOT_TARGET_DEVICES(func) \
>         BOOT_TARGET_DEVICES_MMC(func) \
> +       BOOT_TARGET_DEVICES_QSPI(func) \
>         BOOT_TARGET_DEVICES_PXE(func) \
>         BOOT_TARGET_DEVICES_DHCP(func)
>
> +#ifndef SOCFPGA_BOOT_SETTINGS
> +#define SOCFPGA_BOOT_SETTINGS
> +#endif
> +
>  #include <config_distro_bootcmd.h>
>
>  #ifndef CONFIG_EXTRA_ENV_SETTINGS
> @@ -245,6 +262,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>         "pxefile_addr_r=0x02200000\0" \
>         "ramdisk_addr_r=0x02300000\0" \
>         "socfpga_legacy_reset_compat=1\0" \
> +       SOCFPGA_BOOT_SETTINGS \
>         BOOTENV
>
>  #endif
> diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
> index 028db2a09e..62ad001c4b 100644
> --- a/include/configs/socfpga_cyclone5_socdk.h
> +++ b/include/configs/socfpga_cyclone5_socdk.h
> @@ -14,6 +14,24 @@
>  #define CONFIG_LOADADDR                0x01000000
>  #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
>
> +/* QSPI boot */
> +#define FDT_SIZE               __stringify(0x00010000)
> +#define KERNEL_SIZE            __stringify(0x005d0000)
> +#define QSPI_FDT_ADDR          __stringify(0x00220000)
> +#define QSPI_KERNEL_ADDR       __stringify(0x00230000)
> +
> +#define SOCFPGA_BOOT_SETTINGS \
> +       "fdt_size=" FDT_SIZE "\0" \
> +       "kernel_size=" KERNEL_SIZE "\0" \
> +       "qspi_fdt_addr=" QSPI_FDT_ADDR "\0" \
> +       "qspi_kernel_addr=" QSPI_KERNEL_ADDR "\0" \
> +       "qspiboot=setenv bootargs earlycon " \
> +               "root=/dev/mtdblock1 rw rootfstype=jffs2; " \
> +               "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
> +       "qspiload=sf probe; " \
> +               "sf read ${kernel_addr_r} ${qspi_kernel_addr} ${kernel_size}; " \
> +               "sf read ${fdt_addr_r} ${qspi_fdt_addr} ${fdt_size}\0"
> +
>  /* The rest of the configuration is shared */
>  #include <configs/socfpga_common.h>
>
Any comment on this patch?

Regards
Ley Foon
Marek Vasut March 2, 2020, 10:21 a.m. UTC | #2
On 3/2/20 10:34 AM, Ley Foon Tan wrote:
> On Fri, Feb 21, 2020 at 9:25 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>>
>> Add QSPI boot support to boot target devices list.
>> Platform can provide their own boot settings through SOCFPGA_BOOT_SETTINGS
>> macro if needed.
>>
>> Add SOCFPGA_BOOT_SETTINGS for Cyclone 5.
>>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> ---
>>  include/configs/socfpga_common.h         | 18 ++++++++++++++++++
>>  include/configs/socfpga_cyclone5_socdk.h | 18 ++++++++++++++++++
>>  2 files changed, 36 insertions(+)
>>
>> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
>> index 8d10469e7c..f3ddfca289 100644
>> --- a/include/configs/socfpga_common.h
>> +++ b/include/configs/socfpga_common.h
>> @@ -228,11 +228,28 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>  #define BOOT_TARGET_DEVICES_MMC(func)
>>  #endif
>>
>> +#ifdef CONFIG_CMD_SF
>> +#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
>> +#else
>> +#define BOOT_TARGET_DEVICES_QSPI(func)
>> +#endif
>> +
>> +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
>> +       "bootcmd_qspi=run qspiload; run qspiboot\0"
>> +
>> +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
>> +       "qspi "
>> +
>>  #define BOOT_TARGET_DEVICES(func) \
>>         BOOT_TARGET_DEVICES_MMC(func) \
>> +       BOOT_TARGET_DEVICES_QSPI(func) \
>>         BOOT_TARGET_DEVICES_PXE(func) \
>>         BOOT_TARGET_DEVICES_DHCP(func)
>>
>> +#ifndef SOCFPGA_BOOT_SETTINGS
>> +#define SOCFPGA_BOOT_SETTINGS
>> +#endif
>> +
>>  #include <config_distro_bootcmd.h>
>>
>>  #ifndef CONFIG_EXTRA_ENV_SETTINGS
>> @@ -245,6 +262,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>         "pxefile_addr_r=0x02200000\0" \
>>         "ramdisk_addr_r=0x02300000\0" \
>>         "socfpga_legacy_reset_compat=1\0" \
>> +       SOCFPGA_BOOT_SETTINGS \
>>         BOOTENV
>>
>>  #endif
>> diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
>> index 028db2a09e..62ad001c4b 100644
>> --- a/include/configs/socfpga_cyclone5_socdk.h
>> +++ b/include/configs/socfpga_cyclone5_socdk.h
>> @@ -14,6 +14,24 @@
>>  #define CONFIG_LOADADDR                0x01000000
>>  #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
>>
>> +/* QSPI boot */
>> +#define FDT_SIZE               __stringify(0x00010000)
>> +#define KERNEL_SIZE            __stringify(0x005d0000)
>> +#define QSPI_FDT_ADDR          __stringify(0x00220000)
>> +#define QSPI_KERNEL_ADDR       __stringify(0x00230000)
>> +
>> +#define SOCFPGA_BOOT_SETTINGS \
>> +       "fdt_size=" FDT_SIZE "\0" \
>> +       "kernel_size=" KERNEL_SIZE "\0" \
>> +       "qspi_fdt_addr=" QSPI_FDT_ADDR "\0" \
>> +       "qspi_kernel_addr=" QSPI_KERNEL_ADDR "\0" \
>> +       "qspiboot=setenv bootargs earlycon " \
>> +               "root=/dev/mtdblock1 rw rootfstype=jffs2; " \
>> +               "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
>> +       "qspiload=sf probe; " \
>> +               "sf read ${kernel_addr_r} ${qspi_kernel_addr} ${kernel_size}; " \
>> +               "sf read ${fdt_addr_r} ${qspi_fdt_addr} ${fdt_size}\0"
>> +
>>  /* The rest of the configuration is shared */
>>  #include <configs/socfpga_common.h>
>>
> Any comment on this patch?

Same as A10 very much.
diff mbox series

Patch

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 8d10469e7c..f3ddfca289 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -228,11 +228,28 @@  unsigned int cm_get_qspi_controller_clk_hz(void);
 #define BOOT_TARGET_DEVICES_MMC(func)
 #endif
 
+#ifdef CONFIG_CMD_SF
+#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
+#else
+#define BOOT_TARGET_DEVICES_QSPI(func)
+#endif
+
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+	"bootcmd_qspi=run qspiload; run qspiboot\0"
+
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+	"qspi "
+
 #define BOOT_TARGET_DEVICES(func) \
 	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_QSPI(func) \
 	BOOT_TARGET_DEVICES_PXE(func) \
 	BOOT_TARGET_DEVICES_DHCP(func)
 
+#ifndef SOCFPGA_BOOT_SETTINGS
+#define SOCFPGA_BOOT_SETTINGS
+#endif
+
 #include <config_distro_bootcmd.h>
 
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
@@ -245,6 +262,7 @@  unsigned int cm_get_qspi_controller_clk_hz(void);
 	"pxefile_addr_r=0x02200000\0" \
 	"ramdisk_addr_r=0x02300000\0" \
 	"socfpga_legacy_reset_compat=1\0" \
+	SOCFPGA_BOOT_SETTINGS \
 	BOOTENV
 
 #endif
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index 028db2a09e..62ad001c4b 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -14,6 +14,24 @@ 
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
+/* QSPI boot */
+#define FDT_SIZE		__stringify(0x00010000)
+#define KERNEL_SIZE		__stringify(0x005d0000)
+#define QSPI_FDT_ADDR		__stringify(0x00220000)
+#define QSPI_KERNEL_ADDR	__stringify(0x00230000)
+
+#define SOCFPGA_BOOT_SETTINGS \
+	"fdt_size=" FDT_SIZE "\0" \
+	"kernel_size=" KERNEL_SIZE "\0" \
+	"qspi_fdt_addr=" QSPI_FDT_ADDR "\0" \
+	"qspi_kernel_addr=" QSPI_KERNEL_ADDR "\0" \
+	"qspiboot=setenv bootargs earlycon " \
+		"root=/dev/mtdblock1 rw rootfstype=jffs2; " \
+		"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+	"qspiload=sf probe; " \
+		"sf read ${kernel_addr_r} ${qspi_kernel_addr} ${kernel_size}; " \
+		"sf read ${fdt_addr_r} ${qspi_fdt_addr} ${fdt_size}\0"
+
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>