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bh=aZFvYXy7KKotkvIpGkbqXSJ8c7T6Jg9Ax9BXAeBllpQ=; b=Wzaf9iiwpX6Zarb/UEkhh+Ht8fI4jtkwA2MifTyeSdvYmXAA9Etd/T//2ImenmLVdQ 2bvzWweekqdjaKtSvCeKJnT1jebW6A0dXWDMv0sN+cqO3aEp+J8J8PnpKmtzpqkxy98P vN0DsGQXfNuNrvVZOd1+3hK0FSqyjm63s29AqlqSPV2JxEX3d4klI1mEV+jKPvAx3kgL CxqcjzuVAUORLVtTSoWs6KmbVRHcPL01gdR3Mk1aE7W9B73ENW/9cBfX+iXjNPjvXF+9 965/IoFHu6SuMvrTD5IddSZNhM/RuPVIaL7IsF/aWBd9T6nDLza+OEns62pd/Gf6t662 bj8A== X-Gm-Message-State: APjAAAUIrIRqF7S4gMS0N3lz8Jy1/DrwLmd9/ZXZgBv2IMf9b+HrYCHg y7GdqPMMwHEhsoNaBPd6Vy2piIa+yS6ezg== X-Google-Smtp-Source: APXvYqw07s93RYMyTZofvZTnb2lwvyfDMLI9yfUXGWYyurbWkZ5FuZzM89mYiSOYy4buEmDSACArXA== X-Received: by 2002:ac8:4a16:: with SMTP id x22mr1046832qtq.339.1581401111946; Mon, 10 Feb 2020 22:05:11 -0800 (PST) Received: from localhost.localdomain ([75.102.135.197]) by smtp.gmail.com with ESMTPSA id n4sm1497608qti.55.2020.02.10.22.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2020 22:05:11 -0800 (PST) From: Sean Anderson To: u-boot@lists.denx.de Subject: [PATCH v4 15/17] riscv: Enable cpu clock if it is present Date: Tue, 11 Feb 2020 01:04:23 -0500 Message-Id: <20200211060425.1619471-16-seanga2@gmail.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200211060425.1619471-1-seanga2@gmail.com> References: <20200211060425.1619471-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rick Chen Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.1 at phobos.denx.de X-Virus-Status: Clean The cpu clock is probably already enabled if we are executing code (though we could be executing from a different core). This patch prevents the cpu clock or its parents from being disabled. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng --- This patch was previously submitted on its own as https://patchwork.ozlabs.org/patch/1232420/ Changes in v4: - New drivers/cpu/riscv_cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 5309a49e60..52b74d9e69 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018, Bin Meng + * Copyright (C) 2020, Sean Anderson */ #include @@ -116,6 +117,24 @@ static int riscv_cpu_bind(struct udevice *dev) return 0; } +static int riscv_cpu_probe(struct udevice *dev) +{ + int ret = 0; + struct clk clk; + + /* Get a clock if it exists */ + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return 0; + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret == -ENOSYS || ret == -ENOTSUPP) + return 0; + else + return ret; +} + static const struct cpu_ops riscv_cpu_ops = { .get_desc = riscv_cpu_get_desc, .get_info = riscv_cpu_get_info, @@ -132,6 +151,7 @@ U_BOOT_DRIVER(riscv_cpu) = { .id = UCLASS_CPU, .of_match = riscv_cpu_ids, .bind = riscv_cpu_bind, + .probe = riscv_cpu_probe, .ops = &riscv_cpu_ops, .flags = DM_FLAG_PRE_RELOC, };