From patchwork Wed Jan 29 11:08:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 1230795 X-Patchwork-Delegate: alexey.brodkin@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=synopsys.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=synopsys.com header.i=@synopsys.com header.a=rsa-sha256 header.s=mail header.b=hZcZyIxe; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48712Y0bNrz9sRW for ; Wed, 29 Jan 2020 22:09:09 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 91E6281999; Wed, 29 Jan 2020 12:08:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=synopsys.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=synopsys.com header.i=@synopsys.com header.b="hZcZyIxe"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 32AEE81965; Wed, 29 Jan 2020 12:08:48 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from smtprelay-out1.synopsys.com (smtprelay-out1.synopsys.com [149.117.73.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 73B6D8194A for ; Wed, 29 Jan 2020 12:08:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=synopsys.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Eugeniy.Paltsev@synopsys.com Received: from mailhost.synopsys.com (mdc-mailhost2.synopsys.com [10.225.0.210]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 90F9A4082A; Wed, 29 Jan 2020 11:08:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1580296120; bh=jwhbrJfLaB4zxlzssWRV7zKaT/HDGYWhPl9sgwxqKlI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hZcZyIxeTSvi2BcjA4BRtluqWDJEqKgHthiIVlfEXT0M3hqK17pc+NXscJtVixlMm 8cPfEnXUwzrc3kHzCwUe3I6Wqrt+qQpFElWfZBJM5Fb8rEy9mhN9yjTzesUP7TtATo dzVsXJTh4u0LxkKxDDZ6wEYM9IpQx6iIGEhIUjIaK1yGYkPnzHCXs2ZX10us+tRt1P 5YdI/yiwmbGOai9jg5Cy4x6qofuyxWsUYNDz6iv/vgB9HQdifyE05yhj/eIZ3hvzxv TOuohpSaYLg6OWHNWLMFDFeW5EoJPPj9ZO2ms4jsvgFNWPneMgNuRt4fsRzZdJyNu+ LNDvW09QaSvPA== Received: from paltsev-e7480.internal.synopsys.com (unknown [10.121.8.65]) by mailhost.synopsys.com (Postfix) with ESMTP id BDA97A0073; Wed, 29 Jan 2020 11:08:38 +0000 (UTC) From: Eugeniy Paltsev To: uboot-snps-arc@synopsys.com, Alexey Brodkin Subject: [PATCH 2/2] CLK: HSDK: fix HDMI clock calculation Date: Wed, 29 Jan 2020 14:08:30 +0300 Message-Id: <20200129110830.22004-2-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200129110830.22004-1-Eugeniy.Paltsev@synopsys.com> References: <20200129110830.22004-1-Eugeniy.Paltsev@synopsys.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: u-boot@lists.denx.de, linux-snps-arc@lists.infradead.org, Eugeniy Paltsev Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean HDMI PLL has its own xtal with 27 MHz output but we treat it the same way as other PLLs with 33.33 MHz input. Fix that. Signed-off-by: Eugeniy Paltsev --- drivers/clk/clk-hsdk-cgu.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c index 69e6b24b66c..4637b9fdf15 100644 --- a/drivers/clk/clk-hsdk-cgu.c +++ b/drivers/clk/clk-hsdk-cgu.c @@ -46,17 +46,21 @@ * | |-->|CGU_TUN_IDIV_ROM|-----------> * | |-->|CGU_TUN_IDIV_PWM|-----------> * | - * | ------------ - * |-->| HDMI PLL | - * | ------------ - * | | - * | |-->|CGU_HDMI_IDIV_APB|------> - * | * | ----------- * |-->| DDR PLL | * ----------- * | * |----------------------------> + * + * ------------------ + * | 27.00 MHz xtal | + * ------------------ + * | + * | ------------ + * |-->| HDMI PLL | + * ------------ + * | + * |-->|CGU_HDMI_IDIV_APB|------> */ #define CGU_ARC_IDIV 0x080 @@ -117,7 +121,8 @@ #define CREG_CORE_IF_CLK_DIV_2 0x1 #define MIN_PLL_RATE 100000000 /* 100 MHz */ -#define PARENT_RATE 33333333 /* fixed clock - xtal */ +#define PARENT_RATE_33 33333333 /* fixed clock - xtal */ +#define PARENT_RATE_27 27000000 /* fixed clock - xtal */ #define CGU_MAX_CLOCKS 26 #define CGU_SYS_CLOCKS 16 @@ -237,6 +242,7 @@ struct hsdk_cgu_clk { }; struct hsdk_pll_devdata { + const u32 parent_rate; const struct hsdk_pll_cfg *pll_cfg; int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate, const struct hsdk_pll_cfg *cfg); @@ -248,16 +254,19 @@ static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long, const struct hsdk_pll_cfg *); static const struct hsdk_pll_devdata core_pll_dat = { + .parent_rate = PARENT_RATE_33, .pll_cfg = asdt_pll_cfg, .update_rate = hsdk_pll_core_update_rate, }; static const struct hsdk_pll_devdata sdt_pll_dat = { + .parent_rate = PARENT_RATE_33, .pll_cfg = asdt_pll_cfg, .update_rate = hsdk_pll_comm_update_rate, }; static const struct hsdk_pll_devdata hdmi_pll_dat = { + .parent_rate = PARENT_RATE_27, .pll_cfg = hdmi_pll_cfg, .update_rate = hsdk_pll_comm_update_rate, }; @@ -372,6 +381,7 @@ static ulong pll_get(struct clk *sclk) u64 rate; u32 idiv, fbdiv, odiv; struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); + u32 parent_rate = clk->pll_devdata->parent_rate; val = hsdk_pll_read(clk, CGU_PLL_CTRL); @@ -379,7 +389,7 @@ static ulong pll_get(struct clk *sclk) /* Check if PLL is bypassed */ if (val & CGU_PLL_CTRL_BYPASS) - return PARENT_RATE; + return parent_rate; /* Check if PLL is disabled */ if (val & CGU_PLL_CTRL_PD) @@ -392,7 +402,7 @@ static ulong pll_get(struct clk *sclk) /* output divider = 2^(reg.odiv) */ odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT); - rate = (u64)PARENT_RATE * fbdiv; + rate = (u64)parent_rate * fbdiv; do_div(rate, idiv * odiv); return rate; @@ -490,7 +500,8 @@ static ulong pll_set(struct clk *sclk, ulong rate) } } - pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE); + pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, + clk->pll_devdata->parent_rate); return -EINVAL; }