From patchwork Mon Jan 27 20:01:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Johnson X-Patchwork-Id: 1230028 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=lixil.net Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4860zZ1ZlBz9s1x for ; Tue, 28 Jan 2020 07:03:06 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DDB2E81925; Mon, 27 Jan 2020 21:02:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=lixil.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 3DDCF8191A; Mon, 27 Jan 2020 21:02:19 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from crane.lixil.net (crane.lixil.net [IPv6:2605:2700:1:1045:0:6c:6978:696c]) by phobos.denx.de (Postfix) with ESMTP id 053C481906 for ; Mon, 27 Jan 2020 21:02:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=lixil.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=mrjoel@lixil.net Received: from dark.lixil.net (unknown [IPv6:2601:8c3:4100:b411:acb8:69dc:1c78:fefe]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mrjoel@lixil.net) by crane.lixil.net (Postfix) with ESMTPSA id 4C4F1321FEF; Mon, 27 Jan 2020 13:02:05 -0700 (MST) From: Joel Johnson To: Stefan Roese Subject: [PATCH v5 06/12] arm: mvebu: clearfog: Add SATA mode flags Date: Mon, 27 Jan 2020 13:01:50 -0700 Message-Id: <20200127200156.15173-7-mrjoel@lixil.net> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200127200156.15173-1-mrjoel@lixil.net> References: <20200127200156.15173-1-mrjoel@lixil.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tom Rini , Baruch Siach , u-boot@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean The mPCIe slots on ClearFog Pro and ClearFog Base may be alternately configured for SATA usage. Signed-off-by: Joel Johnson Reviewed-by: Stefan Roese --- v2 changes: - fixed help indentation v3 changes: - none v4 changes: - adjust static SerDes configuration at runtime instead of #ifdef - add setting of swap_rx for SATA (as yet untested on hardware) v5 changes: - make independent of runtime detection --- board/solidrun/clearfog/Kconfig | 17 +++++++++++++++++ board/solidrun/clearfog/clearfog.c | 15 +++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/board/solidrun/clearfog/Kconfig b/board/solidrun/clearfog/Kconfig index c910e17093..44224d903d 100644 --- a/board/solidrun/clearfog/Kconfig +++ b/board/solidrun/clearfog/Kconfig @@ -15,6 +15,23 @@ config TARGET_CLEARFOG_BASE detection via additional EEPROM hardware. This option enables selecting the Base variant for older hardware revisions. +config CLEARFOG_CON3_SATA + bool "Use CON3 slot in SATA mode" + help + Use the CON3 port with SATA protocol instead of the default PCIe. + The ClearFog port allows usage of either mSATA or miniPCIe + modules, but the desired protocol must be configured at build + time since it affects the SerDes topology layout. + +config CLEARFOG_CON2_SATA + bool "Use CON2 slot in SATA mode" + depends on !TARGET_CLEARFOG_BASE + help + Use the CON2 port with SATA protocol instead of the default PCIe. + The ClearFog port allows usage of either mSATA or miniPCIe + modules, but the desired protocol must be configured at build + time since it affects the SerDes topology layout. + config CLEARFOG_SFP_25GB bool "Enable 2.5 Gbps mode for SFP" help diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 064ce4e520..f650e2b40e 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -67,6 +67,21 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB)) board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS; + if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA) && + !IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) { + board_serdes_map[4].serdes_type = SATA2; + board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS; + board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE; + board_serdes_map[4].swap_rx = 1; + } + + if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) { + board_serdes_map[2].serdes_type = SATA1; + board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS; + board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE; + board_serdes_map[2].swap_rx = 1; + } + /* Apply runtime detection changes */ if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) { board_serdes_map[0].serdes_type = PEX0;