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Tue, 31 Dec 2019 06:31:32 +0000 From: Pragnesh Patel To: u-boot@lists.denx.de Subject: [PATCH 1/3] riscv: Add place-holder for FU540 clk and gpio Date: Tue, 31 Dec 2019 12:00:53 +0530 Message-Id: <20191231063055.19412-2-pragnesh.patel@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191231063055.19412-1-pragnesh.patel@sifive.com> References: <20191231063055.19412-1-pragnesh.patel@sifive.com> X-ClientProxiedBy: PN1PR0101CA0021.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:e::31) To MN2PR13MB3616.namprd13.prod.outlook.com (2603:10b6:208:16f::31) MIME-Version: 1.0 Received: from sachinj2-OptiPlex-7010.open-silicon.com (114.143.65.226) by PN1PR0101CA0021.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:e::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2581.11 via Frontend Transport; Tue, 31 Dec 2019 06:31:30 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [114.143.65.226] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e6fcafb1-c019-4695-1e85-08d78dbb13c7 X-MS-TrafficTypeDiagnostic: MN2PR13MB3518: X-LD-Processed: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1,ExtAddr X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2657; 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Signed-off-by: Pragnesh Patel --- arch/riscv/include/asm/arch-fu540/clk.h | 14 ++++++++ arch/riscv/include/asm/arch-fu540/gpio.h | 42 ++++++++++++++++++++++ arch/riscv/include/asm/arch-generic/gpio.h | 32 ++--------------- board/sifive/fu540/Kconfig | 3 ++ 4 files changed, 62 insertions(+), 29 deletions(-) create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h diff --git a/arch/riscv/include/asm/arch-fu540/clk.h b/arch/riscv/include/asm/arch-fu540/clk.h new file mode 100644 index 0000000000..b39f5b55c9 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/clk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 SiFive, Inc. + * + * Authors: + * Pragnesh Patel + */ + +#ifndef _CLK_FU540_H +#define _CLK_FU540_H + +/* Note: This is a placeholder header for driver compilation. */ + +#endif diff --git a/arch/riscv/include/asm/arch-fu540/gpio.h b/arch/riscv/include/asm/arch-fu540/gpio.h new file mode 100644 index 0000000000..f8ddd75852 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/gpio.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 SiFive, Inc. + * + * Authors: + * Sagar Shrikant Kadam + */ + +#ifndef _GPIO_FU540_H +#define _GPIO_FU540_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#define NR_GPIOS 16 + +enum gpio_state { + LOW, + HIGH +}; + +/* Details about a GPIO bank */ +struct sifive_gpio_platdata { + void *base; /* address of registers in physical memory */ +}; + +#endif /* _GPIO_FU540_H */ diff --git a/arch/riscv/include/asm/arch-generic/gpio.h b/arch/riscv/include/asm/arch-generic/gpio.h index dfcb753051..5f0dc0a801 100644 --- a/arch/riscv/include/asm/arch-generic/gpio.h +++ b/arch/riscv/include/asm/arch-generic/gpio.h @@ -3,33 +3,7 @@ * Copyright (C) 2019 SiFive, Inc. */ -#ifndef _GPIO_SIFIVE_H -#define _GPIO_SIFIVE_H +#ifndef __ASM_RISCV_ARCH_GPIO_H +#define __ASM_RISCV_ARCH_GPIO_H -#define GPIO_INPUT_VAL 0x00 -#define GPIO_INPUT_EN 0x04 -#define GPIO_OUTPUT_EN 0x08 -#define GPIO_OUTPUT_VAL 0x0C -#define GPIO_RISE_IE 0x18 -#define GPIO_RISE_IP 0x1C -#define GPIO_FALL_IE 0x20 -#define GPIO_FALL_IP 0x24 -#define GPIO_HIGH_IE 0x28 -#define GPIO_HIGH_IP 0x2C -#define GPIO_LOW_IE 0x30 -#define GPIO_LOW_IP 0x34 -#define GPIO_OUTPUT_XOR 0x40 - -#define NR_GPIOS 16 - -enum gpio_state { - LOW, - HIGH -}; - -/* Details about a GPIO bank */ -struct sifive_gpio_platdata { - void *base; /* address of registers in physical memory */ -}; - -#endif /* _GPIO_SIFIVE_H */ +#endif /* __ASM_RISCV_ARCH_GPIO_H */ diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 5ca21474de..816a135b21 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -12,6 +12,9 @@ config SYS_CPU config SYS_CONFIG_NAME default "sifive-fu540" +config SYS_SOC + default "fu540" + config SYS_TEXT_BASE default 0x80000000 if !RISCV_SMODE default 0x80200000 if RISCV_SMODE