From patchwork Wed Dec 11 13:29:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 1207659 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="egpetjGI"; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47XyTD56CWz9sPh for ; Thu, 12 Dec 2019 00:29:36 +1100 (AEDT) Received: from phobos.denx.de (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B2E0E8148F; Wed, 11 Dec 2019 14:29:27 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="egpetjGI"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9240A80919; Wed, 11 Dec 2019 14:29:25 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.1 required=5.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 33FD980919 for ; Wed, 11 Dec 2019 14:29:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=vigneshr@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBBDTHL9025711; Wed, 11 Dec 2019 07:29:17 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576070957; bh=hAEbkJHhWFGTtHAV4RfUF0MdpUAZeLT34vzGoPZw8T8=; h=From:To:CC:Subject:Date; b=egpetjGI1AsB9B3z+Vg+bo2rNBMTvwy8wCMj0VmxFGAZM/UMh2qfDvwa3ZrXiwT5r eFG7Q81NikmssaguSZf9pJ9gfWmrsx1V6EXwfziB+6RIvYmGEJwUAm+Ju5Gcl4/yCi Wc0RuY0AXigFiA6bX6m2CHYy93vB9mtfXfHu0S3Y= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBBDTHQs072792 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 11 Dec 2019 07:29:17 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Wed, 11 Dec 2019 07:29:17 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Wed, 11 Dec 2019 07:29:17 -0600 Received: from a0132425.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBBDTEbx083651; Wed, 11 Dec 2019 07:29:15 -0600 From: Vignesh Raghavendra To: Jagan Teki Subject: [PATCH] spi: ti_qspi: Add support for CS other than CS0 Date: Wed, 11 Dec 2019 18:59:36 +0530 Message-ID: <20191211132936.25843-1-vigneshr@ti.com> X-Mailer: git-send-email 2.24.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: u-boot@lists.denx.de, Tom Rini Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean Make sure corresponding setup registers are updated depending on CS. This ensures that driver can support QSPI flashes on ChipSelects other than on CS0 Reported-by: Andreas Dannenberg Signed-off-by: Vignesh Raghavendra --- drivers/spi/ti_qspi.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index c3d9e7f2ee0c..664b9cad79d9 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -60,6 +60,8 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_SETUP0_ADDR_SHIFT (8) #define QSPI_SETUP0_DBITS_SHIFT (10) +#define TI_QSPI_SETUP_REG(priv, cs) (&(priv)->base->setup0 + (cs)) + /* ti qspi register set */ struct ti_qspi_regs { u32 pid; @@ -275,8 +277,8 @@ static void ti_qspi_copy_mmap(void *data, void *offset, size_t len) *((unsigned int *)offset) += len; } -static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode, - u8 data_nbits, u8 addr_width, +static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs, + u8 opcode, u8 data_nbits, u8 addr_width, u8 dummy_bytes) { u32 memval = opcode; @@ -296,7 +298,7 @@ static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode, memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT | dummy_bytes << QSPI_SETUP0_DBITS_SHIFT); - writel(memval, &priv->base->setup0); + writel(memval, TI_QSPI_SETUP_REG(priv, cs)); } static int ti_qspi_set_mode(struct udevice *bus, uint mode) @@ -317,13 +319,15 @@ static int ti_qspi_set_mode(struct udevice *bus, uint mode) static int ti_qspi_exec_mem_op(struct spi_slave *slave, const struct spi_mem_op *op) { + struct dm_spi_slave_platdata *slave_plat; struct ti_qspi_priv *priv; struct udevice *bus; + u32 from = 0; + int ret = 0; bus = slave->dev->parent; priv = dev_get_priv(bus); - u32 from = 0; - int ret = 0; + slave_plat = dev_get_parent_platdata(slave->dev); /* Only optimize read path. */ if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN || @@ -335,8 +339,9 @@ static int ti_qspi_exec_mem_op(struct spi_slave *slave, if (from + op->data.nbytes > priv->mmap_size) return -ENOTSUPP; - ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth, - op->addr.nbytes, op->dummy.nbytes); + ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode, + op->data.buswidth, op->addr.nbytes, + op->dummy.nbytes); ti_qspi_copy_mmap((void *)op->data.buf.in, (void *)priv->memory_map + from, op->data.nbytes); @@ -390,7 +395,7 @@ static int ti_qspi_release_bus(struct udevice *dev) writel(0, &priv->base->dc); writel(0, &priv->base->cmd); writel(0, &priv->base->data); - writel(0, &priv->base->setup0); + writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs)); return 0; }