From patchwork Thu Dec 5 23:04:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1204874 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="fNxjstWM"; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47TWdM6T7Rz9sPJ for ; Fri, 6 Dec 2019 10:09:43 +1100 (AEDT) Received: from phobos.denx.de (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 081B68171A; Fri, 6 Dec 2019 00:04:47 +0100 (CET) Authentication-Results: mail.denx.de; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: mail.denx.de; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="fNxjstWM"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3C6538170F; Fri, 6 Dec 2019 00:04:39 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.1 required=5.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-f196.google.com (mail-il1-f196.google.com [209.85.166.196]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5FAE8816F5 for ; Fri, 6 Dec 2019 00:04:35 +0100 (CET) Authentication-Results: mail.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: mail.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-f196.google.com with SMTP id t17so4496762ilm.13 for ; Thu, 05 Dec 2019 15:04:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mSfj1fXnXjajaBtObZvpmAi5ZjBBe0WDJF1lYrIRgRo=; b=fNxjstWMDrPOf0qSKvlj80YNF1Hl4+ERChG/AY0Hk4yqACbBJMWs8b9n+tK3oAPO3l 0J9EFgoBchpcmWxf/1UgnaWSsNcWZG/agyMhGSiYzz1NIUwkrRKWyh1sHtHSHtRHXkXC +l6xSZatwEFP7dgotcICleLh7pE+wBmKHVsbI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mSfj1fXnXjajaBtObZvpmAi5ZjBBe0WDJF1lYrIRgRo=; b=of8+35E078pDQrQWgjCfDYUcNdbdNzC5etmCKBBks/GWj6Xfl/TKQnaBR4ONPHjdGM pNVSfv/WHGmSNY3dkYwOzFzX3mHPOd4YQ1k27e/PcCihx2phgXuPYERkNX948WYAmnAD DRK6ZxgcQTvxnHWkur4iqeKqRuYhXtYiPFwzc7RX0h1KnKajNRAg9/5QzKGX0ds0+Dab OCQ9oEjh3RO30sVUjVNy5s0qHeHlWj5PdhSXJluchE96Jr/BlBpzFhKiTeCu5+FcbCdG kk/DEGu6LTIsqxlCZ3Q1tdohbD6VItzm8bLTeRV64G0uF+xGaqTuJHi1CMgrgHkKzQpw 0Fgg== X-Gm-Message-State: APjAAAV3B/6VCw0vFguLShqViF5a2A8FJuB+z/zYGeSHD8yaNBJNwYpN yJj/OgXWZqr5xkL9rTZOF4RvKVxNnco= X-Google-Smtp-Source: APXvYqwFvKmVB9pZkZcX1uUiM81Hf8lqSJzLvTHMMt3y9r4T9RpHmugGiUXGDCcvhO3J+fyLHMxjNQ== X-Received: by 2002:a92:3a88:: with SMTP id i8mr11261872ilf.254.1575587074176; Thu, 05 Dec 2019 15:04:34 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id x2sm3267095ilk.76.2019.12.05.15.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2019 15:04:33 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Subject: [PATCH 3/4] x86: serial: Add a coreboot serial driver Date: Thu, 5 Dec 2019 16:04:26 -0700 Message-Id: <20191205230428.23497-3-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.393.g34dc348eaf-goog In-Reply-To: <20191205230428.23497-1-sjg@chromium.org> References: <20191205230428.23497-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at mail.denx.de X-Virus-Status: Clean Coreboot can provide information about the serial device in use on a platform. Add a driver that uses this information to produce a working UART. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/serial/Kconfig | 11 ++++++++ drivers/serial/Makefile | 1 + drivers/serial/serial_coreboot.c | 46 ++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+) create mode 100644 drivers/serial/serial_coreboot.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 50710ab998..035ff08059 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -539,6 +539,17 @@ config BCM6345_SERIAL help Select this to enable UART on BCM6345 SoCs. +config COREBOOT_SERIAL + bool "Coreboot UART support" + depends on DM_SERIAL + default y if SYS_COREBOOT + select SYS_NS16550 + help + Select this to enable a ns16550-style UART where the platform data + comes from the coreboot 'sysinfo' tables. This allows U-Boot to have + a serial console on any platform without needing to change the + device tree, etc. + config FSL_LINFLEXUART bool "Freescale Linflex UART support" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 06ee30697d..76b1811510 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o +obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c new file mode 100644 index 0000000000..ccab347514 --- /dev/null +++ b/drivers/serial/serial_coreboot.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * UART support for U-Boot when launched from Coreboot + * + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include + +static int coreboot_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + struct cb_serial *cb_info = lib_sysinfo.serial; + + plat->base = cb_info->baseaddr; + plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0; + plat->reg_width = cb_info->regwidth; + plat->clock = cb_info->input_hertz; + plat->fcr = UART_FCR_DEFVAL; + plat->flags = 0; + if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED) + plat->flags |= NS16550_FLAG_IO; + + return 0; +} + +static const struct udevice_id coreboot_serial_ids[] = { + { .compatible = "coreboot-serial" }, + { }, +}; + +U_BOOT_DRIVER(coreboot_uart) = { + .name = "coreboot_uart", + .id = UCLASS_SERIAL, + .of_match = coreboot_serial_ids, + .priv_auto_alloc_size = sizeof(struct NS16550), + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), + .ofdata_to_platdata = coreboot_ofdata_to_platdata, + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +};