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[U-Boot,v4,20/42] arm: pxa: Drop pxa_wait_ticks()

Message ID 20191114195751.30357-4-sjg@chromium.org
State Accepted
Commit e3107d159c180698bd45511afb76e9ab8f9957fb
Delegated to: Tom Rini
Headers show
Series common: Further reduce common.h | expand

Commit Message

Simon Glass Nov. 14, 2019, 7:57 p.m. UTC 
This function has a similar name to the common wait_ticks(). It is only
used in one place and seems small enough to drop.

Inline it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---

Changes in v4: None
Changes in v3:
- Add new patch to inline pxa_wait_ticks()

Changes in v2: None

 arch/arm/cpu/pxa/pxa2xx.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)
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Patch

diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index 0b28f0a3ef..14fe307c1a 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -39,13 +39,6 @@  int cleanup_before_linux(void)
 	return 0;
 }
 
-void pxa_wait_ticks(int ticks)
-{
-	writel(0, OSCR);
-	while (readl(OSCR) < ticks)
-		asm volatile("" : : : "memory");
-}
-
 inline void writelrb(uint32_t val, uint32_t addr)
 {
 	writel(val, addr);
@@ -136,8 +129,11 @@  void pxa2xx_dram_init(void)
 
 	writelrb(CONFIG_SYS_MDCNFG_VAL &
 		~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
+
 	/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
-	pxa_wait_ticks(0x300);
+	writel(0, OSCR);
+	while (readl(OSCR) < 0x300)
+		asm volatile("" : : : "memory");
 
 	/*
 	 * 8) Trigger a number (usually 8) refresh cycles by attempting