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[U-Boot,v2,06/10] spl: cache: Allow cache drivers in SPL

Message ID 20191114055230.20289-7-uboot@andestech.com
State Accepted
Commit 31dae22faa65534cb71631f6c74cbdcf4930a339
Delegated to: Andes
Headers show
Series RISC-V AX25-AE350 support SPL | expand

Commit Message

Andes Nov. 14, 2019, 5:52 a.m. UTC 
From: Rick Chen <rick@andestech.com>

When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
---
 common/spl/Kconfig | 7 +++++++
 drivers/Makefile   | 1 +
 2 files changed, 8 insertions(+)
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Patch

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 8f0ba8e..9ed7a42 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -439,6 +439,13 @@  config SPL_FIT_IMAGE_TINY
 	  ensure this information is available to the next image
 	  invoked).
 
+config SPL_CACHE_SUPPORT
+	bool "Support CACHE drivers"
+	help
+	  Enable CACHE drivers in SPL. These drivers can keep data so that
+	  future requests for that data can be served faster. Enable this option
+	  to build the drivers in drivers/cache as part of an SPL build.
+
 config SPL_CPU_SUPPORT
 	bool "Support CPU drivers"
 	help
diff --git a/drivers/Makefile b/drivers/Makefile
index 0befedd..8c29b1e 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -31,6 +31,7 @@  ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_BUILD
 
 obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
+obj-$(CONFIG_SPL_CACHE_SUPPORT) += cache/
 obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/