From patchwork Fri Nov 8 19:53:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1192148 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="U40AW/RX"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 478rvs4Lpjz9sPL for ; Sat, 9 Nov 2019 07:09:29 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0CF72C21F19; Fri, 8 Nov 2019 20:04:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2F059C21F1A; Fri, 8 Nov 2019 19:56:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 51091C21F71; Fri, 8 Nov 2019 19:56:48 +0000 (UTC) Received: from mail-io1-f68.google.com (mail-io1-f68.google.com [209.85.166.68]) by lists.denx.de (Postfix) with ESMTPS id A9E92C21F53 for ; Fri, 8 Nov 2019 19:55:25 +0000 (UTC) Received: by mail-io1-f68.google.com with SMTP id q83so7669908iod.1 for ; Fri, 08 Nov 2019 11:55:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3hv0kOWi4vOT++xw9bL9QaCM/Pa5cAgI10dvNRdb0i8=; b=U40AW/RXp7OCJiSHGY4L/y5XkRIVuXrb9UXqHRm7XvNX91WAIjaprxLX2pPCzgBDkh nyuluwSX4Ogftqhgv6wBuA/kum++76WeJ+IWCZLS0hFM183SXWYj4nhAVxipJFnkePL7 KUmjGPKiTUS7kqugHjMtHGCputD4+RaMJZz9M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3hv0kOWi4vOT++xw9bL9QaCM/Pa5cAgI10dvNRdb0i8=; b=cKjHR0jrHyt8s1mpF1METe27qe+1jADtxdJUKF4O96z7bVAoBl9jhaIinyT5Y58YHe XvjAedtWqxOx0yx5F+92FkaHxaEzbvMf0o9B0S2G4/l3A3JaOH3DxwRpZFNyqeiwJ+SP 3aKtXM4ivzhKhnJul+GJze2+xo/seUbLwrN0v7WUm46Y3GLvcU4XjGLt8gx/d/CxPG3c CDnDHBo3InE+AiPKqaZMdUStINoVyELzxonFgrnfiT1HK2PcVWyxDBvbGrjDsrYeHxpC mYU61FhXPDUXjC1UKSNniwjMMJmFrAHCtLtTLoxemUAlMgWTTyIPis+vBG+t4xSSe69c l6CA== X-Gm-Message-State: APjAAAW/0JEoTs3a/FDYFEKlcqgwAqepfkiQ2H4cpMb6T/QGHVjejrbc oTwwg1YpSK2AqLQ4THZnNPiZwo5z8vlTDg== X-Google-Smtp-Source: APXvYqxT00Qd2vVmotiAMMxWCKTwy9GCwuY6EOlE6rJeRHDlg33JPuvWeDg7Ipv7VLHH48gJXbV9rg== X-Received: by 2002:a02:1788:: with SMTP id 130mr12517084jah.82.1573242924416; Fri, 08 Nov 2019 11:55:24 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id l205sm622306ill.50.2019.11.08.11.55.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 11:55:24 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Fri, 8 Nov 2019 12:53:34 -0700 Message-Id: <20191108195348.110648-4-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.rc1.363.gb1bccd3e3d-goog In-Reply-To: <20191108195348.110648-1-sjg@chromium.org> References: <20191108195348.110648-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Tom Rini , Albert Aribaud , Andy Fleming , Stefan Roese Subject: [U-Boot] [PATCH v2 27/41] arm: powerpc: Tidy up code style for cache functions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Remove the unwanted space before the bracket. Signed-off-by: Simon Glass Reviewed-by: Tom Rini --- Changes in v2: None arch/arm/lib/cache-cp15.c | 12 ++++++------ arch/microblaze/cpu/cache.c | 18 +++++++++++------- board/armltd/integrator/integrator.c | 2 +- board/cobra5272/flash.c | 12 ++++++------ include/common.h | 2 +- post/lib_powerpc/cpu.c | 6 +++--- 6 files changed, 28 insertions(+), 24 deletions(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index b2913e8165..fc6d69134c 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -247,17 +247,17 @@ static void cache_disable(uint32_t cache_bit) #endif #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -void icache_enable (void) +void icache_enable(void) { return; } -void icache_disable (void) +void icache_disable(void) { return; } -int icache_status (void) +int icache_status(void) { return 0; /* always off */ } @@ -279,17 +279,17 @@ int icache_status(void) #endif #if CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void dcache_enable (void) +void dcache_enable(void) { return; } -void dcache_disable (void) +void dcache_disable(void) { return; } -int dcache_status (void) +int dcache_status(void) { return 0; /* always off */ } diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index eebeb37830..94114555ff 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -8,7 +8,7 @@ #include #include -int dcache_status (void) +int dcache_status(void) { int i = 0; int mask = 0x80; @@ -18,7 +18,7 @@ int dcache_status (void) return i; } -int icache_status (void) +int icache_status(void) { int i = 0; int mask = 0x20; @@ -28,28 +28,32 @@ int icache_status (void) return i; } -void icache_enable (void) { +void icache_enable(void) +{ MSRSET(0x20); } -void icache_disable(void) { +void icache_disable(void) +{ /* we are not generate ICACHE size -> flush whole cache */ flush_cache(0, 32768); MSRCLR(0x20); } -void dcache_enable (void) { +void dcache_enable(void) +{ MSRSET(0x80); } -void dcache_disable(void) { +void dcache_disable(void) +{ #ifdef XILINX_USE_DCACHE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); #endif MSRCLR(0x80); } -void flush_cache (ulong addr, ulong size) +void flush_cache(ulong addr, ulong size) { int i; for (i = 0; i < size; i += 4) diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 0a2baa7297..f0fbe2b417 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -109,7 +109,7 @@ extern void cm_remap(void); writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS); #endif - icache_enable (); + icache_enable(); return 0; } diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index e5edc2a040..9bf824889a 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -164,8 +164,8 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) * chip is in programming mode. */ - cflag = icache_status (); - icache_disable (); + cflag = icache_status(); + icache_disable(); iflag = disable_interrupts (); printf ("\n"); @@ -237,7 +237,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) enable_interrupts (); if (cflag) - icache_enable (); + icache_enable(); return rc; } @@ -267,8 +267,8 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) * chip is in programming mode. */ - cflag = icache_status (); - icache_disable (); + cflag = icache_status(); + icache_disable(); iflag = disable_interrupts (); MEM_FLASH_ADDR1 = CMD_UNLOCK1; @@ -303,7 +303,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) enable_interrupts (); if (cflag) - icache_enable (); + icache_enable(); return rc; } diff --git a/include/common.h b/include/common.h index 3f6a95d7e0..82b1abe698 100644 --- a/include/common.h +++ b/include/common.h @@ -189,7 +189,7 @@ int testdram(void); int icache_status (void); void icache_enable (void); void icache_disable(void); -int dcache_status (void); +int dcache_status(void); void dcache_enable (void); void dcache_disable(void); void mmu_disable(void); diff --git a/post/lib_powerpc/cpu.c b/post/lib_powerpc/cpu.c index 109be38e16..6713039330 100644 --- a/post/lib_powerpc/cpu.c +++ b/post/lib_powerpc/cpu.c @@ -57,12 +57,12 @@ ulong cpu_post_makecr (long v) int cpu_post_test (int flags) { - int ic = icache_status (); + int ic = icache_status(); int ret = 0; WATCHDOG_RESET(); if (ic) - icache_disable (); + icache_disable(); if (ret == 0) ret = cpu_post_test_cmp (); @@ -110,7 +110,7 @@ int cpu_post_test (int flags) WATCHDOG_RESET(); if (ic) - icache_enable (); + icache_enable(); WATCHDOG_RESET();