From patchwork Wed Oct 30 08:16:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 1186589 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4731Wk1WdDz9sPd for ; Wed, 30 Oct 2019 19:16:49 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 867B6C21DB6; Wed, 30 Oct 2019 08:16:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 202FFC21CB1; Wed, 30 Oct 2019 08:16:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D35FAC21C51; Wed, 30 Oct 2019 08:16:40 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.134]) by lists.denx.de (Postfix) with ESMTPS id 3E58EC21BE5 for ; Wed, 30 Oct 2019 08:16:40 +0000 (UTC) Received: from localhost (unknown [192.168.167.225]) by lucky1.263xmail.com (Postfix) with ESMTP id 0074448A1A for ; Wed, 30 Oct 2019 16:16:37 +0800 (CST) X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P13859T139952820045568S1572423391692618_; Wed, 30 Oct 2019 16:16:38 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <6c22d027371f1539b9a53988741db4c5> X-RL-SENDER: andy.yan@rock-chips.com X-SENDER: yxj@rock-chips.com X-LOGIN-NAME: andy.yan@rock-chips.com X-FST-TO: yk@rock-chips.com X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Andy Yan To: kever.yang@rock-chips.com Date: Wed, 30 Oct 2019 16:16:28 +0800 Message-Id: <20191030081629.8812-4-andy.yan@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191030081629.8812-1-andy.yan@rock-chips.com> References: <20191030081140.8635-1-andy.yan@rock-chips.com> <20191030081629.8812-1-andy.yan@rock-chips.com> Cc: u-boot@lists.denx.de, Andy Yan Subject: [U-Boot] [PATCH v2 8/9] rockchip: rk3308: Add support for ROC-RK3308-CC board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Andy Yan --- Changes in v2: - Add board ROC-rk3308-CC arch/arm/mach-rockchip/rk3308/Kconfig | 5 ++ board/firefly/firefly-rk3308/Kconfig | 15 ++++ board/firefly/firefly-rk3308/MAINTAINERS | 5 ++ board/firefly/firefly-rk3308/Makefile | 7 ++ board/firefly/firefly-rk3308/roc_rk3308_cc.c | 82 ++++++++++++++++++++ configs/roc-rk3308-cc_defconfig | 77 ++++++++++++++++++ 6 files changed, 191 insertions(+) create mode 100644 board/firefly/firefly-rk3308/Kconfig create mode 100644 board/firefly/firefly-rk3308/MAINTAINERS create mode 100644 board/firefly/firefly-rk3308/Makefile create mode 100644 board/firefly/firefly-rk3308/roc_rk3308_cc.c create mode 100644 configs/roc-rk3308-cc_defconfig diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index c74d1fc7f1..b9fdfe2e95 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -4,6 +4,10 @@ config TARGET_EVB_RK3308 bool "EVB_RK3308" select BOARD_LATE_INIT +config TARGET_ROC_RK3308_CC + bool "Firefly roc-rk3308-cc" + select BOARD_LATE_INIT + config SYS_SOC default "rk3308" @@ -18,5 +22,6 @@ config ROCKCHIP_BOOT_MODE_REG source "board/rockchip/evb_rk3308/Kconfig" +source "board/firefly/firefly-rk3308/Kconfig" endif diff --git a/board/firefly/firefly-rk3308/Kconfig b/board/firefly/firefly-rk3308/Kconfig new file mode 100644 index 0000000000..7d4d189e54 --- /dev/null +++ b/board/firefly/firefly-rk3308/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ROC_RK3308_CC + +config SYS_BOARD + default "firefly-rk3308" + +config SYS_VENDOR + default "firefly" + +config SYS_CONFIG_NAME + default "evb_rk3308" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/firefly/firefly-rk3308/MAINTAINERS b/board/firefly/firefly-rk3308/MAINTAINERS new file mode 100644 index 0000000000..8670d8c6a8 --- /dev/null +++ b/board/firefly/firefly-rk3308/MAINTAINERS @@ -0,0 +1,5 @@ +ROC-RK3308-CC +M: Andy Yan +S: Maintained +F: board/firefly/firefly-rk3308/roc_rk3308_cc.c +F: configs/roc-rk3308-cc_defconfig diff --git a/board/firefly/firefly-rk3308/Makefile b/board/firefly/firefly-rk3308/Makefile new file mode 100644 index 0000000000..587d2e6f44 --- /dev/null +++ b/board/firefly/firefly-rk3308/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2018 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += roc_rk3308_cc.o diff --git a/board/firefly/firefly-rk3308/roc_rk3308_cc.c b/board/firefly/firefly-rk3308/roc_rk3308_cc.c new file mode 100644 index 0000000000..1deaa39516 --- /dev/null +++ b/board/firefly/firefly-rk3308/roc_rk3308_cc.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_DEBUG_UART) +#define GRF_BASE 0xff000000 + +enum { + GPIO1C7_SHIFT = 8, + GPIO1C7_MASK = GENMASK(11, 8), + GPIO1C7_GPIO = 0, + GPIO1C7_UART1_RTSN, + GPIO1C7_UART2_TX_M0, + GPIO1C7_SPI2_MOSI, + GPIO1C7_JTAG_TMS, + + GPIO1C6_SHIFT = 4, + GPIO1C6_MASK = GENMASK(7, 4), + GPIO1C6_GPIO = 0, + GPIO1C6_UART1_CTSN, + GPIO1C6_UART2_RX_M0, + GPIO1C6_SPI2_MISO, + GPIO1C6_JTAG_TCLK, + + GPIO4D3_SHIFT = 6, + GPIO4D3_MASK = GENMASK(7, 6), + GPIO4D3_GPIO = 0, + GPIO4D3_SDMMC_D3, + GPIO4D3_UART2_TX_M1, + + GPIO4D2_SHIFT = 4, + GPIO4D2_MASK = GENMASK(5, 4), + GPIO4D2_GPIO = 0, + GPIO4D2_SDMMC_D2, + GPIO4D2_UART2_RX_M1, + + UART2_IO_SEL_SHIFT = 2, + UART2_IO_SEL_MASK = GENMASK(3, 2), + UART2_IO_SEL_M0 = 0, + UART2_IO_SEL_M1, + UART2_IO_SEL_USB, +}; + +void board_debug_uart_init(void) +{ + static struct rk3308_grf * const grf = (void *)GRF_BASE; + + /* Enable early UART2 channel m0 on the rk3308 */ + rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK, + UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT); + rk_clrsetreg(&grf->gpio1ch_iomux, + GPIO1C6_MASK | GPIO1C7_MASK, + GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT | + GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT); +} +#endif + +#define KEY_DOWN_MIN_VAL 0 +#define KEY_DOWN_MAX_VAL 30 + +int rockchip_dnl_key_pressed(void) +{ + unsigned int val; + + + if (adc_channel_single_shot("saradc", 1, &val)) { + printf("%s read adc key val failed\n", __func__); + return false; + } + + if (val >= KEY_DOWN_MIN_VAL && val <= KEY_DOWN_MAX_VAL) + return true; + else + return false; +} diff --git a/configs/roc-rk3308-cc_defconfig b/configs/roc-rk3308-cc_defconfig new file mode 100644 index 0000000000..82ebe6a786 --- /dev/null +++ b/configs/roc-rk3308-cc_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00600000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3308=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_ROC_RK3308_CC=y +CONFIG_SPL_STACK_R_ADDR=0xc00000 +CONFIG_DEBUG_UART_BASE=0xFF0C0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +# CONFIG_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_LZ4=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set