From patchwork Sat Oct 26 00:26:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184512 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="pDbzz69P"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MMb4ZJcz9sPc for ; Sat, 26 Oct 2019 11:30:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 558A6C21EC9; Sat, 26 Oct 2019 00:28:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CCEBDC21EBF; Sat, 26 Oct 2019 00:27:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 949F6C21DDC; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id 60B4CC21C51 for ; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 17C0F22EEB; Sat, 26 Oct 2019 02:27:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049634; bh=PUPOM3HIJLQI0PH7yw4nDDocReMmcGg2eiifw7bd9DU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pDbzz69PG21eut08NxhvaC1U85HiA8OvIlasr1EL8T8uFEBbRppT1LH/K0Dm4uUxR jjlQ0U7U/o2IiCSjSUn3mZUX3HKfkMni5eUctUqZBisXRsI0TNBl+P4+gDmg48J7Mu tn+ZN4IG5moh5qexQ0z8j3N43lh7G4QfM9xJNRRU= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:26 +0200 Message-Id: <20191026002630.25865-6-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 5/9] phy: atheros: don't overwrite debug register values X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Instead of doing a hard write, do a read-modify-write. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 113374f03f..4b7a1fb9c4 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -12,10 +12,10 @@ #define AR803x_PHY_DEBUG_DATA_REG 0x1e #define AR803x_DEBUG_REG_5 0x5 -#define AR803x_RGMII_TX_CLK_DLY 0x100 +#define AR803x_RGMII_TX_CLK_DLY BIT(8) #define AR803x_DEBUG_REG_0 0x0 -#define AR803x_RGMII_RX_CLK_DLY 0x8000 +#define AR803x_RGMII_RX_CLK_DLY BIT(15) static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg) { @@ -74,16 +74,16 @@ static int ar803x_delay_config(struct phy_device *phydev) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - ret = ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, - AR803x_RGMII_TX_CLK_DLY); + ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, + 0, AR803x_RGMII_TX_CLK_DLY); if (ret < 0) return ret; } if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - ret = ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_0, - AR803x_RGMII_RX_CLK_DLY); + ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_0, + 0, AR803x_RGMII_RX_CLK_DLY); if (ret < 0) return ret; }