From patchwork Sat Oct 26 00:26:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184510 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="spyIOOIk"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MLH4SzQz9sPc for ; Sat, 26 Oct 2019 11:29:27 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5ADCCC21ECE; Sat, 26 Oct 2019 00:27:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AF36BC21DD9; Sat, 26 Oct 2019 00:27:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 01BA6C21C6A; Sat, 26 Oct 2019 00:27:13 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id 98C4BC21C6A for ; Sat, 26 Oct 2019 00:27:13 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 4A0F722EE9; Sat, 26 Oct 2019 02:27:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049633; bh=E9gwEBZIKM+BuqhIOrMJ85sQYbBqQgufhKiqFwdhxzk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=spyIOOIkheOXSCge9KuKDAoCZjcP/CetndUjV5g2s024tvfF7No/850Yz1q29pjxd pv4nszAVyABxokl48YRwKEm5zVAXTTFjTrsq6dCkAxooNkLWtrK7uHrghs94skHUBS PRLiBnFe2UGaSOH72XvmGoXD8eiQ66TWSxwO7TqE= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:22 +0200 Message-Id: <20191026002630.25865-2-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 1/9] phy: atheros: introduce debug read and write functions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 72 ++++++++++++++++++++++++++++----------- 1 file changed, 53 insertions(+), 19 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 3783d155e7..b25aa02108 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -17,11 +17,52 @@ #define AR803x_DEBUG_REG_0 0x0 #define AR803x_RGMII_RX_CLK_DLY 0x8000 +static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg) +{ + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + reg); + if (ret < 0) + return ret; + + return phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG); +} + +static int ar803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 val) +{ + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + reg); + if (ret < 0) + return ret; + + return phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + val); +} + +static int ar803x_debug_reg_mask(struct phy_device *phydev, u16 reg, + u16 clear, u16 set) +{ + int val; + + val = ar803x_debug_reg_read(phydev, reg); + if (val < 0) + return val; + + val &= 0xffff; + val &= ~clear; + val |= set; + + return phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + val); +} + static int ar8021_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); + ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, 0x3D47); phydev->supported = phydev->drv->features; return 0; @@ -31,18 +72,14 @@ static int ar8031_config(struct phy_device *phydev) { if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, - AR803x_DEBUG_REG_5); - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, - AR803x_RGMII_TX_CLK_DLY); + ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, + AR803x_RGMII_TX_CLK_DLY); } if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, - AR803x_DEBUG_REG_0); - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, - AR803x_RGMII_RX_CLK_DLY); + ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_0, + AR803x_RGMII_RX_CLK_DLY); } phydev->supported = phydev->drv->features; @@ -63,24 +100,21 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); + ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, + 0, AR803x_RGMII_TX_CLK_DLY); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { - /* select debug reg 5 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5); /* enable tx delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100); + ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, + AR803x_RGMII_TX_CLK_DLY); } if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) { - /* select debug reg 0 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0); /* enable rx delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000); + ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_0, + AR803x_RGMII_RX_CLK_DLY); } phydev->supported = phydev->drv->features;