From patchwork Mon Oct 21 09:25:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 1180420 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="LRE+mnL2"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46xWTj4X3Tz9sCJ for ; Mon, 21 Oct 2019 20:26:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 407E8C21E3E; Mon, 21 Oct 2019 09:25:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 33487C21E2F; Mon, 21 Oct 2019 09:25:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8ECB3C21E3E; Mon, 21 Oct 2019 09:25:46 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lists.denx.de (Postfix) with ESMTPS id 10274C21E50 for ; Mon, 21 Oct 2019 09:25:45 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9L9Pg3d088442; Mon, 21 Oct 2019 04:25:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571649942; bh=dBFgjj89lHLxiWOleYPHiL2kMMAbmxwHHbEFJlYJQQk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LRE+mnL2PQ8dxFL9m+PrilvnvUAaBw1czPTvfHA2VZNyazqa0EjlTdvNpjZgv0G5z +biBRWkPgGMCIoC6DoQlXKu7S7AbQZAxxJC9M3UIxrvyBlILQq7CPbj3pH837cxthQ rxi8R/pSRchkjlgZdgT/lM1qGLIuNaAAj6tVc2uI= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9L9PR2t038722 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 21 Oct 2019 04:25:27 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 21 Oct 2019 04:25:17 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 21 Oct 2019 04:25:17 -0500 Received: from a0393675ula.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9L9P6qa122020; Mon, 21 Oct 2019 04:25:09 -0500 From: Keerthy To: , , Date: Mon, 21 Oct 2019 14:55:06 +0530 Message-ID: <20191021092515.25608-2-j-keerthy@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191021092515.25608-1-j-keerthy@ti.com> References: <20191021092515.25608-1-j-keerthy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: t-kristo@ti.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 01/10] misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tero Kristo Adaptive Voltage Scaling is a technology used in TI SoCs to optimize the operating voltage based on characterization data written to efuse during production. Add a driver to support this feature for K3 line of SoCs, initially for AM65x. Signed-off-by: Tero Kristo Signed-off-by: Keerthy --- Changes in v2: * Avoided creation of new UCLASS & placed the driver under misc. drivers/misc/Kconfig | 9 ++ drivers/misc/Makefile | 1 + drivers/misc/k3_avs.c | 366 ++++++++++++++++++++++++++++++++++++++++++ include/k3-avs.h | 28 ++++ 4 files changed, 404 insertions(+) create mode 100644 drivers/misc/k3_avs.c create mode 100644 include/k3-avs.h diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index ba50893b43..f6147238a4 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -412,4 +412,13 @@ config IHS_FPGA by the devices. This driver supports both CON and CPU variants of the devices, depending on the device tree entry. +config K3_AVS0 + depends on ARCH_K3 && SPL_DM_REGULATOR + bool "AVS class 0 support for K3 devices" + help + K3 devices have the optimized voltage values for the main voltage + domains stored in efuse within the VTM IP. This driver reads the + optimized voltage from the efuse, so that it can be programmed + to the PMIC on board. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 0001d105ba..74d01ef392 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -65,3 +65,4 @@ obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o +obj-$(CONFIG_K3_AVS0) += k3_avs.o diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c new file mode 100644 index 0000000000..dd7fc3d585 --- /dev/null +++ b/drivers/misc/k3_avs.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' K3 Clas 0 Adaptive Voltage Scaling driver + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#define AM6_VTM_DEVINFO(i) (priv->base + 0x100 + 0x20 * (i)) +#define AM6_VTM_OPPVID_VD(i) (priv->base + 0x104 + 0x20 * (i)) + +#define AM6_VTM_AVS0_SUPPORTED BIT(12) + +#define AM6_VTM_OPP_SHIFT(opp) (8 * (opp)) +#define AM6_VTM_OPP_MASK 0xff + +#define VD_FLAG_INIT_DONE BIT(0) + +struct k3_avs_privdata { + void *base; + struct vd_config *vd_config; +}; + +struct opp { + u32 freq; + u32 volt; +}; + +struct vd_data { + int id; + u8 opp; + u8 flags; + int dev_id; + int clk_id; + struct opp opps[NUM_OPPS]; + struct udevice *supply; +}; + +struct vd_config { + struct vd_data *vds; + u32 (*efuse_xlate)(struct k3_avs_privdata *priv, int idx, int opp); +}; + +static struct k3_avs_privdata *k3_avs_priv; + +/** + * am6_efuse_voltage: read efuse voltage from VTM + * @priv: driver private data + * @idx: VD to read efuse for + * @opp: opp id to read + * + * Reads efuse value for the specified OPP, and converts the register + * value to a voltage. Returns the voltage in uV, or 0 if nominal voltage + * should be used. + * + * Efuse val to volt conversion logic: + * + * val > 171 volt increments in 20mV steps with base 171 => 1.66V + * val between 115 to 11 increments in 10mV steps with base 115 => 1.1V + * val between 15 to 115 increments in 5mV steps with base 15 => .6V + * val between 1 to 15 increments in 20mv steps with base 0 => .3V + * val 0 is invalid + */ +static u32 am6_efuse_xlate(struct k3_avs_privdata *priv, int idx, int opp) +{ + u32 val = readl(AM6_VTM_OPPVID_VD(idx)); + + val >>= AM6_VTM_OPP_SHIFT(opp); + val &= AM6_VTM_OPP_MASK; + + if (!val) + return 0; + + if (val > 171) + return 1660000 + 20000 * (val - 171); + + if (val > 115) + return 1100000 + 10000 * (val - 115); + + if (val > 15) + return 600000 + 5000 * (val - 15); + + return 300000 + 20000 * val; +} + +static int k3_avs_program_voltage(struct k3_avs_privdata *priv, + struct vd_data *vd, + int opp_id) +{ + u32 volt = vd->opps[opp_id].volt; + struct vd_data *vd2; + + if (!vd->supply) + return -ENODEV; + + vd->opp = opp_id; + vd->flags |= VD_FLAG_INIT_DONE; + + /* Take care of ganged rails and pick the Max amongst them*/ + for (vd2 = priv->vd_config->vds; vd2->id >= 0; vd2++) { + if (vd == vd2) + continue; + + if (vd2->supply != vd->supply) + continue; + + if (vd2->opps[vd2->opp].volt > volt) + volt = vd2->opps[vd2->opp].volt; + + vd2->flags |= VD_FLAG_INIT_DONE; + } + + return regulator_set_value(vd->supply, volt); +} + +static struct vd_data *get_vd(struct k3_avs_privdata *priv, int idx) +{ + struct vd_data *vd; + + for (vd = priv->vd_config->vds; vd->id >= 0 && vd->id != idx; vd++) + ; + + if (vd->id < 0) + return NULL; + + return vd; +} + +/** + * k3_avs_set_opp: Sets the voltage for an arbitrary VD rail + * @dev: AVS device + * @vdd_id: voltage domain ID + * @opp_id: OPP ID + * + * Programs the desired OPP value for the defined voltage rail. This + * should be called from board files if reconfiguration is desired. + * Returns 0 on success, negative error value on failure. + */ +int k3_avs_set_opp(struct udevice *dev, int vdd_id, int opp_id) +{ + struct k3_avs_privdata *priv = dev_get_priv(dev); + struct vd_data *vd; + + vd = get_vd(priv, vdd_id); + if (!vd) + return -EINVAL; + + return k3_avs_program_voltage(priv, vd, opp_id); +} + +static int match_opp(struct vd_data *vd, u32 freq) +{ + struct opp *opp; + int opp_id; + + for (opp_id = 0; opp_id < NUM_OPPS; opp_id++) { + opp = &vd->opps[opp_id]; + if (opp->freq == freq) + return opp_id; + } + + printf("No matching OPP found for freq %d.\n", freq); + + return -EINVAL; +} + +/** + * k3_avs_notify_freq: Notify clock rate change towards AVS subsystem + * @dev_id: Device ID for the clock to be changed + * @clk_id: Clock ID for the clock to be changed + * @freq: New frequency for clock + * + * Checks if the provided clock is the MPU clock or not, if not, return + * immediately. If MPU clock is provided, maps the provided MPU frequency + * towards an MPU OPP, and programs the voltage to the regulator. Return 0 + * on success, negative error value on failure. + */ +int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq) +{ + int opp_id; + struct k3_avs_privdata *priv = k3_avs_priv; + struct vd_data *vd; + + for (vd = priv->vd_config->vds; vd->id >= 0; vd++) { + if (vd->dev_id != dev_id || vd->clk_id != clk_id) + continue; + + opp_id = match_opp(vd, freq); + if (opp_id < 0) + return opp_id; + + vd->opp = opp_id; + return k3_avs_program_voltage(priv, vd, opp_id); + } + + return -EINVAL; +} + +static int k3_avs_configure(struct udevice *dev, struct k3_avs_privdata *priv) +{ + struct vd_config *conf; + int ret; + char pname[20]; + struct vd_data *vd; + + conf = (void *)dev_get_driver_data(dev); + + priv->vd_config = conf; + + for (vd = conf->vds; vd->id >= 0; vd++) { + sprintf(pname, "vdd-supply-%d", vd->id); + ret = device_get_supply_regulator(dev, pname, &vd->supply); + if (ret) + dev_warn(dev, "supply not found for VD%d.\n", vd->id); + + sprintf(pname, "ti,default-opp-%d", vd->id); + ret = dev_read_u32_default(dev, pname, -1); + if (ret != -1) + vd->opp = ret; + } + + return 0; +} + +/** + * k3_avs_probe: parses VD info from VTM, and re-configures the OPP data + * + * Parses all VDs on a device calculating the AVS class-0 voltages for them, + * and updates the vd_data based on this. The vd_data itself shall be used + * to program the required OPPs later on. Returns 0 on success, negative + * error value on failure. + */ +static int k3_avs_probe(struct udevice *dev) +{ + int opp_id; + u32 volt; + struct opp *opp; + struct k3_avs_privdata *priv; + struct vd_data *vd; + int ret; + + priv = dev_get_priv(dev); + + k3_avs_priv = priv; + + ret = k3_avs_configure(dev, priv); + if (ret) + return ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENODEV; + + for (vd = priv->vd_config->vds; vd->id >= 0; vd++) { + if (!(readl(AM6_VTM_DEVINFO(vd->id)) & + AM6_VTM_AVS0_SUPPORTED)) { + dev_warn(dev, "AVS-class 0 not supported for VD%d\n", + vd->id); + continue; + } + + for (opp_id = 0; opp_id < NUM_OPPS; opp_id++) { + opp = &vd->opps[opp_id]; + + if (!opp->freq) + continue; + + volt = priv->vd_config->efuse_xlate(priv, vd->id, + opp_id); + if (volt) + opp->volt = volt; + } + } + + for (vd = priv->vd_config->vds; vd->id >= 0; vd++) { + if (vd->flags & VD_FLAG_INIT_DONE) + continue; + + k3_avs_program_voltage(priv, vd, vd->opp); + } + + return 0; +} + +static struct vd_data am654_vd_data[] = { + { + .id = AM6_VDD_CORE, + .dev_id = 82, /* AM6_DEV_CBASS0 */ + .clk_id = 0, /* main sysclk0 */ + .opp = AM6_OPP_NOM, + .opps = { + [AM6_OPP_NOM] = { + .volt = 1000000, + .freq = 250000000, /* CBASS0 */ + }, + }, + }, + { + .id = AM6_VDD_MPU0, + .dev_id = 202, /* AM6_DEV_COMPUTE_CLUSTER_A53_0 */ + .clk_id = 0, /* ARM clock */ + .opp = AM6_OPP_NOM, + .opps = { + [AM6_OPP_NOM] = { + .volt = 1000000, + .freq = 800000000, + }, + [AM6_OPP_OD] = { + .volt = 1100000, + .freq = 1000000000, + }, + [AM6_OPP_TURBO] = { + .volt = 1220000, + .freq = 1100000000, + }, + }, + }, + { + .id = AM6_VDD_MPU1, + .opp = AM6_OPP_NOM, + .dev_id = 204, /* AM6_DEV_COMPUTE_CLUSTER_A53_2 */ + .clk_id = 0, /* ARM clock */ + .opps = { + [AM6_OPP_NOM] = { + .volt = 1000000, + .freq = 800000000, + }, + [AM6_OPP_OD] = { + .volt = 1100000, + .freq = 1000000000, + }, + [AM6_OPP_TURBO] = { + .volt = 1220000, + .freq = 1100000000, + }, + }, + }, + { .id = -1 }, +}; + +static struct vd_config am654_vd_config = { + .efuse_xlate = am6_efuse_xlate, + .vds = am654_vd_data, +}; + +static const struct udevice_id k3_avs_ids[] = { + { .compatible = "ti,am654-avs", .data = (ulong)&am654_vd_config }, + {} +}; + +U_BOOT_DRIVER(k3_avs) = { + .name = "k3_avs", + .of_match = k3_avs_ids, + .id = UCLASS_MISC, + .probe = k3_avs_probe, + .priv_auto_alloc_size = sizeof(struct k3_avs_privdata), +}; diff --git a/include/k3-avs.h b/include/k3-avs.h new file mode 100644 index 0000000000..9867481617 --- /dev/null +++ b/include/k3-avs.h @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' K3 Adaptive Voltage Scaling driver + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + * + */ + +#ifndef _K3_AVS0_ +#define _K3_AVS0_ + +#define AM6_VDD_WKUP 0 +#define AM6_VDD_MCU 1 +#define AM6_VDD_CORE 2 +#define AM6_VDD_MPU0 3 +#define AM6_VDD_MPU1 4 + +#define NUM_OPPS 4 + +#define AM6_OPP_NOM 1 +#define AM6_OPP_OD 2 +#define AM6_OPP_TURBO 3 + +int k3_avs_set_opp(struct udevice *dev, int vdd_id, int opp_id); +int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq); + +#endif