@@ -804,6 +804,7 @@ int clock_init(void)
init_wdog_clk();
clock_enable(CCGR_TSENSOR, 1);
+ clock_enable(CCGR_OCOTP, 1);
return 0;
}
@@ -204,14 +204,21 @@ u32 get_cpu_rev(void)
} else {
if (reg == CHIP_REV_1_0) {
/*
- * For B0 chip, the DIGPROG is not updated, still TO1.0.
- * we have to check ROM version further
+ * For B0 chip, the DIGPROG is not updated,
+ * it is still TO1.0. we have to check ROM
+ * version or OCOTP_READ_FUSE_DATA.
+ * 0xff0055aa is magic number for B1.
*/
- rom_version = readl((void __iomem *)ROM_VERSION_A0);
- if (rom_version != CHIP_REV_1_0) {
- rom_version = readl((void __iomem *)ROM_VERSION_B0);
- if (rom_version >= CHIP_REV_2_0)
- reg = CHIP_REV_2_0;
+ if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
+ reg = CHIP_REV_2_1;
+ } else {
+ rom_version =
+ readl((void __iomem *)ROM_VERSION_A0);
+ if (rom_version != CHIP_REV_1_0) {
+ rom_version = readl((void __iomem *)ROM_VERSION_B0);
+ if (rom_version == CHIP_REV_2_0)
+ reg = CHIP_REV_2_0;
+ }
}
}
}
The i.MX8MQ B1 uses OCOTP_HW_OCOTP_READ_FUSE_DATA register for chip id. It returns a magic number 0xff0055aa. update get_cpu_rev to support it, and enable ocotp clock to access ocotp. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/mach-imx/imx8m/clock_imx8mq.c | 1 + arch/arm/mach-imx/imx8m/soc.c | 21 ++++++++++++++------- 2 files changed, 15 insertions(+), 7 deletions(-)