diff mbox series

[U-Boot,4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

Message ID 20191004223043.18127-5-dalon.westergreen@linux.intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series ARM: socfpga: arria10: Cleanup devicetree and | expand

Commit Message

Dalon L Westergreen Oct. 4, 2019, 10:30 p.m. UTC
From: Dalon Westergreen <dalon.westergreen@intel.com>

Generic handoff devicetree include uses a header generated by
the qts-filter-a10.sh script in mach-socfpga.  The script
creates the header based on design specific implementations
for clock and pinmux configurations.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 .../dts/socfpga_arria10_handoff_u-boot.dtsi   | 232 ++++++++++++++++--
 1 file changed, 216 insertions(+), 16 deletions(-)

Comments

Marek Vasut Oct. 4, 2019, 11:51 p.m. UTC | #1
On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Generic handoff devicetree include uses a header generated by
> the qts-filter-a10.sh script in mach-socfpga.  The script
> creates the header based on design specific implementations
> for clock and pinmux configurations.

[...]

> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi

[...]

> -	clock_manager@0xffd04000 {
> +	clkmgr@0xffd04000 {
> +		compatible = "altr,socfpga-a10-clk-init";
> +		reg = <0xffd04000 0x00000200>;
> +		reg-names = "soc_clock_manager_OCP_SLV";
>  		u-boot,dm-pre-reloc;
>  
>  		mainpll {
> +			vco0-psrc = <MAINPLLGRP_VCO0_PSRC>;
> +			vco1-denom = <MAINPLLGRP_VCO1_DENOM>;
> +			vco1-numer = <MAINPLLGRP_VCO1_NUMER>;

But these bits are board-specific , they shouldn't be in common DT.
Dalon L Westergreen Oct. 5, 2019, 11:19 p.m. UTC | #2
On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <dalon.westergreen@intel.com>
> > Generic handoff devicetree include uses a header generated bythe qts-filter-
> > a10.sh script in mach-socfpga.  The scriptcreates the header based on design
> > specific implementationsfor clock and pinmux configurations.
> 
> [...]
> > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> 
> [...]
> > -	clock_manager@0xffd04000 {+	clkmgr@0xffd04000 {+		compatible =
> > "altr,socfpga-a10-clk-init";+		reg = <0xffd04000 0x00000200>;+	
> > 	reg-names = "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-
> > reloc;  		mainpll {+			vco0-psrc =
> > <MAINPLLGRP_VCO0_PSRC>;+			vco1-denom =
> > <MAINPLLGRP_VCO1_DENOM>;+			vco1-numer =
> > <MAINPLLGRP_VCO1_NUMER>;
> 
> But these bits are board-specific , they shouldn't be in common DT.

This common dtsi requires that the top level u-boot.dtsi include the board
specific header.  The format
and #define names are in fact common.

--dalon
Marek Vasut Oct. 6, 2019, 1:44 p.m. UTC | #3
On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
>> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>>> From: Dalon Westergreen <dalon.westergreen@intel.com>
>>> Generic handoff devicetree include uses a header generated bythe qts-filter-
>>> a10.sh script in mach-socfpga.  The scriptcreates the header based on design
>>> specific implementationsfor clock and pinmux configurations.
>>
>> [...]
>>> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>>> b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>>
>> [...]
>>> -	clock_manager@0xffd04000 {+	clkmgr@0xffd04000 {+		compatible =
>>> "altr,socfpga-a10-clk-init";+		reg = <0xffd04000 0x00000200>;+	
>>> 	reg-names = "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-
>>> reloc;  		mainpll {+			vco0-psrc =
>>> <MAINPLLGRP_VCO0_PSRC>;+			vco1-denom =
>>> <MAINPLLGRP_VCO1_DENOM>;+			vco1-numer =
>>> <MAINPLLGRP_VCO1_NUMER>;
>>
>> But these bits are board-specific , they shouldn't be in common DT.
> 
> This common dtsi requires that the top level u-boot.dtsi include the board
> specific header.  The format
> and #define names are in fact common.

OK, I now see what you're doing here. Can you explain that in a bit more
detail in the commit message ?

Basically socfpga_board.h is included socfpga_board.dts , and then the
preprocessor correctly expands the values from socfpga_board.h in the
socfpga_board.dts , so this works for multiple boards too ?
Dalon L Westergreen Oct. 6, 2019, 5:44 p.m. UTC | #4
On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > From: Dalon Westergreen <dalon.westergreen@intel.com>Generic handoff
> > > > devicetree include uses a header generated bythe qts-filter-a10.sh
> > > > script in mach-socfpga.  The scriptcreates the header based on
> > > > designspecific implementationsfor clock and pinmux configurations.
> > > 
> > > [...]
> > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > 
> > > [...]
> > > > -	clock_manager@0xffd04000 {+	clkmgr@0xffd04000 {+		
> > > > compatible ="altr,socfpga-a10-clk-init";+		reg =
> > > > <0xffd04000 0x00000200>;+		reg-names =
> > > > "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-reloc;  		
> > > > mainpll {+			vco0-psrc =<MAINPLLGRP_VCO0_PSRC>;+		
> > > > 	vco1-denom =<MAINPLLGRP_VCO1_DENOM>;+			vco1-
> > > > numer =<MAINPLLGRP_VCO1_NUMER>;
> > > 
> > > But these bits are board-specific , they shouldn't be in common DT.
> > 
> > This common dtsi requires that the top level u-boot.dtsi include the
> > boardspecific header.  The formatand #define names are in fact common.
> 
> OK, I now see what you're doing here. Can you explain that in a bit moredetail
> in the commit message ?
> Basically socfpga_board.h is included socfpga_board.dts , and then
> thepreprocessor correctly expands the values from socfpga_board.h in
> thesocfpga_board.dts , so this works for multiple boards too ?

Exactly.  Will add more detail in the commit message, and slim down the included
clocks in
the u-boot.dtsi
Simon Goldschmidt Oct. 6, 2019, 6:05 p.m. UTC | #5
Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
>> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
>>> On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
>>>> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>>>>> From: Dalon Westergreen <
>>>>> dalon.westergreen@intel.com
>>>>>  <mailto:dalon.westergreen@intel.com>
>>>>> >
>>>>> Generic handoff devicetree include uses a header generated bythe qts-filter-
>>>>> a10.sh script in mach-socfpga.  The scriptcreates the header based on design
>>>>> specific implementationsfor clock and pinmux configurations.
>>>>
>>>> [...]
>>>>> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>>>>> b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>>>>
>>>> [...]
>>>>> -	clock_manager@0xffd04000 {+	clkmgr@0xffd04000 {+		compatible =
>>>>> "altr,socfpga-a10-clk-init";+		reg = <0xffd04000 0x00000200>;+	
>>>>> 	reg-names = "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-
>>>>> reloc;  		mainpll {+			vco0-psrc =
>>>>> <MAINPLLGRP_VCO0_PSRC>;+			vco1-denom =
>>>>> <MAINPLLGRP_VCO1_DENOM>;+			vco1-numer =
>>>>> <MAINPLLGRP_VCO1_NUMER>;
>>>>
>>>> But these bits are board-specific , they shouldn't be in common DT.
>>>
>>> This common dtsi requires that the top level u-boot.dtsi include the board
>>> specific header.  The format
>>> and #define names are in fact common.
>>
>> OK, I now see what you're doing here. Can you explain that in a bit more
>> detail in the commit message ?
>>
>> Basically socfpga_board.h is included socfpga_board.dts , and then the
>> preprocessor correctly expands the values from socfpga_board.h in the
>> socfpga_board.dts , so this works for multiple boards too ?
> 
> Exactly. Will add more detail in the commit message, and slim down the 
> included clocks in
> the u-boot.dtsi

I'm (still) working on a series to bring gen5 completely to devicetree, 
so that the 'qts' directories can be removed. I chose a different 
approach however, in that I generated everything into a '-handoff.dtsi' 
file (*). I'd be happy if we could find a common mechanism for all 
socfpga sub-archs. How does S10/Agilex handle this?

(*): Gen5 has the downside that we're low on memory in SPL (regarding 
DM), and as we require large binary arrays there, I chose to encode the 
binary blob arrays in host byte order so that they could be used 
in-place instead of copying them from BE (dtb) to LE (stack/heap). Maybe 
that doesn't fit A10/S10/Agilex anyway?

Regards,
Simon
Dalon L Westergreen Oct. 6, 2019, 11:04 p.m. UTC | #6
On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > > > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > > > From: Dalon Westergreen <dalon.westergreen@intel.com
> > > > > >  <mailto:dalon.westergreen@intel.com>
> > > > > > Generic handoff devicetree include uses a header generated bythe
> > > > > > qts-filter-a10.sh script in mach-socfpga.  The scriptcreates the
> > > > > > header based on designspecific implementationsfor clock and pinmux
> > > > > > configurations.
> > > > > 
> > > > > [...]
> > > > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > > > 
> > > > > [...]
> > > > > > -	clock_manager@0xffd04000 {+	clkmgr@0xffd04000 {+		comp
> > > > > > atible ="altr,socfpga-a10-clk-init";+		reg =
> > > > > > <0xffd04000 0x00000200>;+		reg-names =
> > > > > > "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-reloc;  	
> > > > > > 	mainpll {+			vco0-psrc =<MAINPLLGRP_VCO0_PSRC>;+	
> > > > > > 		vco1-denom =<MAINPLLGRP_VCO1_DENOM>;+			
> > > > > > vco1-numer =<MAINPLLGRP_VCO1_NUMER>;
> > > > > 
> > > > > But these bits are board-specific , they shouldn't be in common DT.
> > > > 
> > > > This common dtsi requires that the top level u-boot.dtsi include the
> > > > boardspecific header.  The formatand #define names are in fact common.
> > > 
> > > OK, I now see what you're doing here. Can you explain that in a bit
> > > moredetail in the commit message ?
> > > Basically socfpga_board.h is included socfpga_board.dts , and then
> > > thepreprocessor correctly expands the values from socfpga_board.h in
> > > thesocfpga_board.dts , so this works for multiple boards too ?
> > 
> > Exactly. Will add more detail in the commit message, and slim down the
> > included clocks inthe u-boot.dtsi
> 
> I'm (still) working on a series to bring gen5 completely to devicetree, so
> that the 'qts' directories can be removed. I chose a different approach
> however, in that I generated everything into a '-handoff.dtsi' file (*). I'd
> be happy if we could find a common mechanism for all socfpga sub-archs. How
> does S10/Agilex handle this?
> (*): Gen5 has the downside that we're low on memory in SPL (regarding DM), and
> as we require large binary arrays there, I chose to encode the binary blob
> arrays in host byte order so that they could be used in-place instead of
> copying them from BE (dtb) to LE (stack/heap). Maybe that doesn't fit
> A10/S10/Agilex anyway?

S10/Agilex are entirely different.  The onchip ram is loaded with any
configuration data bythe secure device manager.  There is no need to modify the
dts for any io/pll/bridgeconfiguration. 
A10 is better than cv/av in that is requires far less configuration data, and no
dataregarding the dram is needed.  Also, there is no binary parsing required for
extractingthe required data, hence the simple qts-filter-a10.sh.  
I think a -handoff.dtsi is a good approach, but why not do the same thing i do
here anduse a header file for the config data.  that way the -handoff.dtsi can
be common and theheader only needs to be included in the toplevel -u-boot.dtsi?
--dalon
> Regards,Simon
Dalon L Westergreen Oct. 6, 2019, 11:06 p.m. UTC | #7
On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > From: Dalon Westergreen <dalon.westergreen@intel.com>Generic handoff
> > > > devicetree include uses a header generated bythe qts-filter-a10.sh
> > > > script in mach-socfpga.  The scriptcreates the header based on
> > > > designspecific implementationsfor clock and pinmux configurations.
> > > 
> > > [...]
> > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > 
> > > [...]
> > > > -	clock_manager@0xffd04000 {+	clkmgr@0xffd04000 {+		
> > > > compatible ="altr,socfpga-a10-clk-init";+		reg =
> > > > <0xffd04000 0x00000200>;+		reg-names =
> > > > "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-reloc;  		
> > > > mainpll {+			vco0-psrc =<MAINPLLGRP_VCO0_PSRC>;+		
> > > > 	vco1-denom =<MAINPLLGRP_VCO1_DENOM>;+			vco1-
> > > > numer =<MAINPLLGRP_VCO1_NUMER>;
> > > 
> > > But these bits are board-specific , they shouldn't be in common DT.
> > 
> > This common dtsi requires that the top level u-boot.dtsi include the
> > boardspecific header.  The formatand #define names are in fact common.
> 
> OK, I now see what you're doing here. Can you explain that in a bit moredetail
> in the commit message ?
> Basically socfpga_board.h is included socfpga_board.dts , and then
> thepreprocessor correctly expands the values from socfpga_board.h in
> thesocfpga_board.dts , so this works for multiple boards too ?

oh, and yes, it does work for multiple boards, i have already tested this.

--dalon
Dalon L Westergreen Oct. 7, 2019, 2:34 p.m. UTC | #8
On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > > > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > > > From: Dalon Westergreen <dalon.westergreen@intel.com
> > > > > >  <mailto:dalon.westergreen@intel.com>
> > > > > > Generic handoff devicetree include uses a header generated bythe
> > > > > > qts-filter-a10.sh script in mach-socfpga.  The scriptcreates the
> > > > > > header based on designspecific implementationsfor clock and pinmux
> > > > > > configurations.
> > > > > 
> > > > > [...]
> > > > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > > > 
> > > > > [...]
> > > > > > -	clock_manager@0xffd04000 {+	clkmgr@0xffd04000 {+		comp
> > > > > > atible ="altr,socfpga-a10-clk-init";+		reg =
> > > > > > <0xffd04000 0x00000200>;+		reg-names =
> > > > > > "soc_clock_manager_OCP_SLV"; 		u-boot,dm-pre-reloc;  	
> > > > > > 	mainpll {+			vco0-psrc =<MAINPLLGRP_VCO0_PSRC>;+	
> > > > > > 		vco1-denom =<MAINPLLGRP_VCO1_DENOM>;+			
> > > > > > vco1-numer =<MAINPLLGRP_VCO1_NUMER>;
> > > > > 
> > > > > But these bits are board-specific , they shouldn't be in common DT.
> > > > 
> > > > This common dtsi requires that the top level u-boot.dtsi include the
> > > > boardspecific header.  The formatand #define names are in fact common.
> > > 
> > > OK, I now see what you're doing here. Can you explain that in a bit
> > > moredetail in the commit message ?
> > > Basically socfpga_board.h is included socfpga_board.dts , and then
> > > thepreprocessor correctly expands the values from socfpga_board.h in
> > > thesocfpga_board.dts , so this works for multiple boards too ?
> > 
> > Exactly. Will add more detail in the commit message, and slim down the
> > included clocks inthe u-boot.dtsi
> 
> I'm (still) working on a series to bring gen5 completely to devicetree, so
> that the 'qts' directories can be removed. I chose a different approach
> however, in that I generated everything into a '-handoff.dtsi' file (*). I'd
> be happy if we could find a common mechanism for all socfpga sub-archs. How
> does S10/Agilex handle this?
> (*): Gen5 has the downside that we're low on memory in SPL (regarding DM), and
> as we require large binary arrays there, I chose to encode the binary blob
> arrays in host byte order so that they could be used in-place instead of
> copying them from BE (dtb) to LE (stack/heap). Maybe that doesn't fit
> A10/S10/Agilex anyway?

Can you share your patch set with me, privately or otherwise, just so we can
take a similarapproach in the devicetree?
Also, have you looked at the bsp-editor python source that generates the
"generated" filesfrom the bsp-editor?  
19.1std/647/linux64/ip/altera/preloader/scripts
I am hoping to replace these with a script included in the u-boot
source.  iocsr.py doesa bunch of binary parsing.
--dalon
> Regards,Simon
Simon Goldschmidt Oct. 7, 2019, 2:45 p.m. UTC | #9
There's something wrong with your mailer: indentation of replies doesn't seem
to work. It gets kind of hard to read who wrote what...

On Mon, Oct 7, 2019 at 4:34 PM Dalon L Westergreen
<dalon.westergreen@linux.intel.com> wrote:
>
> On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
>
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
>
> On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
>
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
>
> On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
>
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>
> From: Dalon Westergreen <
>
> dalon.westergreen@intel.com
>
>
>  <mailto:
>
> dalon.westergreen@intel.com
>
> >
>
>
> Generic handoff devicetree include uses a header generated bythe qts-filter-
>
> a10.sh script in mach-socfpga.  The scriptcreates the header based on design
>
> specific implementationsfor clock and pinmux configurations.
>
>
> [...]
>
> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>
> b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>
>
> [...]
>
> - clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+ compatible =
>
> "altr,socfpga-a10-clk-init";+ reg = <0xffd04000 0x00000200>;+
>
> reg-names = "soc_clock_manager_OCP_SLV"; u-boot,dm-pre-
>
> reloc;   mainpll {+ vco0-psrc =
>
> <MAINPLLGRP_VCO0_PSRC>;+ vco1-denom =
>
> <MAINPLLGRP_VCO1_DENOM>;+ vco1-numer =
>
> <MAINPLLGRP_VCO1_NUMER>;
>
>
> But these bits are board-specific , they shouldn't be in common DT.
>
>
> This common dtsi requires that the top level u-boot.dtsi include the board
>
> specific header.  The format
>
> and #define names are in fact common.
>
>
> OK, I now see what you're doing here. Can you explain that in a bit more
>
> detail in the commit message ?
>
>
> Basically socfpga_board.h is included socfpga_board.dts , and then the
>
> preprocessor correctly expands the values from socfpga_board.h in the
>
> socfpga_board.dts , so this works for multiple boards too ?
>
>
> Exactly. Will add more detail in the commit message, and slim down the
>
> included clocks in
>
> the u-boot.dtsi
>
>
> I'm (still) working on a series to bring gen5 completely to devicetree,
>
> so that the 'qts' directories can be removed. I chose a different
>
> approach however, in that I generated everything into a '-handoff.dtsi'
>
> file (*). I'd be happy if we could find a common mechanism for all
>
> socfpga sub-archs. How does S10/Agilex handle this?
>
>
> (*): Gen5 has the downside that we're low on memory in SPL (regarding
>
> DM), and as we require large binary arrays there, I chose to encode the
>
> binary blob arrays in host byte order so that they could be used
>
> in-place instead of copying them from BE (dtb) to LE (stack/heap). Maybe
>
> that doesn't fit A10/S10/Agilex anyway?
>
>
> Can you share your patch set with me, privately or otherwise, just so we can take a similar
> approach in the devicetree?

Give me a week max. and I'll send the series as RFC.

>
> Also, have you looked at the bsp-editor python source that generates the "generated" files
> from the bsp-editor?
>
> 19.1std/647/linux64/ip/altera/preloader/scripts

No, I mainly focused on the U-Boot part for now. I just wrote a C program
that did the conversion from 'official generated' files to DTS...

>
> I am hoping to replace these with a script included in the u-boot source. iocsr.py does
> a bunch of binary parsing.

Right, a direct conversion from compilation output to U-Boot would be better.
However, that would require Intel to keep that output consistent!

Regards,
Simon

>
> --dalon
>
>
> Regards,
>
> Simon
Dalon L Westergreen Oct. 8, 2019, 5:08 p.m. UTC | #10
On Mon, 2019-10-07 at 16:45 +0200, Simon Goldschmidt wrote:
> There's something wrong with your mailer: indentation of replies doesn't
> seemto work. It gets kind of hard to read who wrote what...
> On Mon, Oct 7, 2019 at 4:34 PM Dalon L Westergreen<
> dalon.westergreen@linux.intel.com> wrote:
> > On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> > Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <
> > dalon.westergreen@intel.com
> > 
> > 
> >  <mailto:
> > dalon.westergreen@intel.com
> > 
> > 
> > Generic handoff devicetree include uses a header generated bythe qts-filter-
> > a10.sh script in mach-socfpga.  The scriptcreates the header based on design
> > specific implementationsfor clock and pinmux configurations.
> > 
> > [...]
> > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > 
> > [...]
> > - clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+ compatible =
> > "altr,socfpga-a10-clk-init";+ reg = <0xffd04000 0x00000200>;+
> > reg-names = "soc_clock_manager_OCP_SLV"; u-boot,dm-pre-
> > reloc;   mainpll {+ vco0-psrc =
> > <MAINPLLGRP_VCO0_PSRC>;+ vco1-denom =
> > <MAINPLLGRP_VCO1_DENOM>;+ vco1-numer =
> > <MAINPLLGRP_VCO1_NUMER>;
> > 
> > But these bits are board-specific , they shouldn't be in common DT.
> > 
> > This common dtsi requires that the top level u-boot.dtsi include the board
> > specific header.  The format
> > and #define names are in fact common.
> > 
> > OK, I now see what you're doing here. Can you explain that in a bit more
> > detail in the commit message ?
> > 
> > Basically socfpga_board.h is included socfpga_board.dts , and then the
> > preprocessor correctly expands the values from socfpga_board.h in the
> > socfpga_board.dts , so this works for multiple boards too ?
> > 
> > Exactly. Will add more detail in the commit message, and slim down the
> > included clocks in
> > the u-boot.dtsi
> > 
> > I'm (still) working on a series to bring gen5 completely to devicetree,
> > so that the 'qts' directories can be removed. I chose a different
> > approach however, in that I generated everything into a '-handoff.dtsi'
> > file (*). I'd be happy if we could find a common mechanism for all
> > socfpga sub-archs. How does S10/Agilex handle this?
> > 
> > (*): Gen5 has the downside that we're low on memory in SPL (regarding
> > DM), and as we require large binary arrays there, I chose to encode the
> > binary blob arrays in host byte order so that they could be used
> > in-place instead of copying them from BE (dtb) to LE (stack/heap). Maybe
> > that doesn't fit A10/S10/Agilex anyway?
> > 
> > Can you share your patch set with me, privately or otherwise, just so we can
> > take a similarapproach in the devicetree?
> 
> Give me a week max. and I'll send the series as RFC.
> > Also, have you looked at the bsp-editor python source that generates the
> > "generated" filesfrom the bsp-editor?
> > 19.1std/647/linux64/ip/altera/preloader/scripts
> 
> No, I mainly focused on the U-Boot part for now. I just wrote a C programthat
> did the conversion from 'official generated' files to DTS...
> > I am hoping to replace these with a script included in the u-boot source.
> > iocsr.py doesa bunch of binary parsing.
> 
> Right, a direct conversion from compilation output to U-Boot would be
> better.However, that would require Intel to keep that output consistent!
It should be consistent at this point.  i would not worry about that.
> Regards,Simon
> > --dalon
> > 
> > Regards,
> > Simon
diff mbox series

Patch

diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
index ef215230c2..69854352a0 100644
--- a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -1,91 +1,291 @@ 
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 
 / {
-	chosen {
-		u-boot,dm-pre-reloc;
-	};
-
 	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
 		u-boot,dm-pre-reloc;
 
-		altera_arria10_hps_eosc1 {
+		altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <EOSC1_CLK_HZ>;
+			clock-output-names = "altera_arria10_hps_eosc1-clk";
 			u-boot,dm-pre-reloc;
 		};
 
-		altera_arria10_hps_cb_intosc_ls {
+		altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <CB_INTOSC_LS_CLK_HZ>;
+			clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
 			u-boot,dm-pre-reloc;
 		};
 
-		altera_arria10_hps_f2h_free {
+		/* Clock source: altera_arria10_hps_f2h_free */
+		altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <F2H_FREE_CLK_HZ>;
+			clock-output-names = "altera_arria10_hps_f2h_free-clk";
 			u-boot,dm-pre-reloc;
 		};
 	};
 
-	clock_manager@0xffd04000 {
+	clkmgr@0xffd04000 {
+		compatible = "altr,socfpga-a10-clk-init";
+		reg = <0xffd04000 0x00000200>;
+		reg-names = "soc_clock_manager_OCP_SLV";
 		u-boot,dm-pre-reloc;
 
 		mainpll {
+			vco0-psrc = <MAINPLLGRP_VCO0_PSRC>;
+			vco1-denom = <MAINPLLGRP_VCO1_DENOM>;
+			vco1-numer = <MAINPLLGRP_VCO1_NUMER>;
+			mpuclk-cnt = <MAINPLLGRP_MPUCLK_CNT>;
+			mpuclk-src = <MAINPLLGRP_MPUCLK_SRC>;
+			nocclk-cnt = <MAINPLLGRP_NOCCLK_CNT>;
+			nocclk-src = <MAINPLLGRP_NOCCLK_SRC>;
+			cntr2clk-cnt = <MAINPLLGRP_CNTR2CLK_CNT>;
+			cntr3clk-cnt = <MAINPLLGRP_CNTR3CLK_CNT>;
+			cntr4clk-cnt = <MAINPLLGRP_CNTR4CLK_CNT>;
+			cntr5clk-cnt = <MAINPLLGRP_CNTR5CLK_CNT>;
+			cntr6clk-cnt = <MAINPLLGRP_CNTR6CLK_CNT>;
+			cntr7clk-cnt = <MAINPLLGRP_CNTR7CLK_CNT>;
+			cntr7clk-src = <MAINPLLGRP_CNTR7CLK_SRC>;
+			cntr8clk-cnt = <MAINPLLGRP_CNTR8CLK_CNT>;
+			cntr9clk-cnt = <MAINPLLGRP_CNTR9CLK_CNT>;
+			cntr9clk-src = <MAINPLLGRP_CNTR9CLK_SRC>;
+			cntr15clk-cnt = <MAINPLLGRP_CNTR15CLK_CNT>;
+			nocdiv-l4mainclk = <MAINPLLGRP_NOCDIV_L4MAINCLK>;
+			nocdiv-l4mpclk = <MAINPLLGRP_NOCDIV_L4MPCLK>;
+			nocdiv-l4spclk = <MAINPLLGRP_NOCDIV_L4SPCLK>;
+			nocdiv-csatclk = <MAINPLLGRP_NOCDIV_CSATCLK>;
+			nocdiv-cstraceclk = <MAINPLLGRP_NOCDIV_CSTRACECLK>;
+			nocdiv-cspdbgclk = <MAINPLLGRP_NOCDIV_CSPDBGCLK>;
 			u-boot,dm-pre-reloc;
 		};
 
 		perpll {
+			vco0-psrc = <PERPLLGRP_VCO0_PSRC>;
+			vco1-denom = <PERPLLGRP_VCO1_DENOM>;
+			vco1-numer = <PERPLLGRP_VCO1_NUMER>;
+			cntr2clk-cnt = <PERPLLGRP_CNTR2CLK_CNT>;
+			cntr2clk-src = <PERPLLGRP_CNTR2CLK_SRC>;
+			cntr3clk-cnt = <PERPLLGRP_CNTR3CLK_CNT>;
+			cntr3clk-src = <PERPLLGRP_CNTR3CLK_SRC>;
+			cntr4clk-cnt = <PERPLLGRP_CNTR4CLK_CNT>;
+			cntr4clk-src = <PERPLLGRP_CNTR4CLK_SRC>;
+			cntr5clk-cnt = <PERPLLGRP_CNTR5CLK_CNT>;
+			cntr5clk-src = <PERPLLGRP_CNTR5CLK_SRC>;
+			cntr6clk-cnt = <PERPLLGRP_CNTR6CLK_CNT>;
+			cntr6clk-src = <PERPLLGRP_CNTR6CLK_SRC>;
+			cntr7clk-cnt = <PERPLLGRP_CNTR7CLK_CNT>;
+			cntr8clk-cnt = <PERPLLGRP_CNTR8CLK_CNT>;
+			cntr8clk-src = <PERPLLGRP_CNTR8CLK_SRC>;
+			cntr9clk-cnt = <PERPLLGRP_CNTR9CLK_CNT>;
+			emacctl-emac0sel = <PERPLLGRP_EMACCTL_EMAC0SEL>;
+			emacctl-emac1sel = <PERPLLGRP_EMACCTL_EMAC1SEL>;
+			emacctl-emac2sel = <PERPLLGRP_EMACCTL_EMAC2SEL>;
+			gpiodiv-gpiodbclk = <PERPLLGRP_GPIODIV_GPIODBCLK>;
 			u-boot,dm-pre-reloc;
 		};
 
 		alteragrp {
+			nocclk = <ALTERAGRP_NOCCLK>;
+			mpuclk = <ALTERAGRP_MPUCLK>;
 			u-boot,dm-pre-reloc;
 		};
 	};
 
-	pinmux@0xffd07000 {
+	i_io48_pin_mux: pinmux@0xffd07000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pinctrl-single";
+		reg = <0xffd07000 0x00000800>;
+		reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
 		u-boot,dm-pre-reloc;
 
 		shared {
+			reg = <0xffd07000 0x00000200>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x0000000f>;
+			pinctrl-single,pins =
+				<0x00000000 PINMUX_SHARED_IO_Q1_1_SEL>,
+				<0x00000004 PINMUX_SHARED_IO_Q1_2_SEL>,
+				<0x00000008 PINMUX_SHARED_IO_Q1_3_SEL>,
+				<0x0000000c PINMUX_SHARED_IO_Q1_4_SEL>,
+				<0x00000010 PINMUX_SHARED_IO_Q1_5_SEL>,
+				<0x00000014 PINMUX_SHARED_IO_Q1_6_SEL>,
+				<0x00000018 PINMUX_SHARED_IO_Q1_7_SEL>,
+				<0x0000001c PINMUX_SHARED_IO_Q1_8_SEL>,
+				<0x00000020 PINMUX_SHARED_IO_Q1_9_SEL>,
+				<0x00000024 PINMUX_SHARED_IO_Q1_10_SEL>,
+				<0x00000028 PINMUX_SHARED_IO_Q1_11_SEL>,
+				<0x0000002c PINMUX_SHARED_IO_Q1_12_SEL>,
+				<0x00000030 PINMUX_SHARED_IO_Q2_1_SEL>,
+				<0x00000034 PINMUX_SHARED_IO_Q2_2_SEL>,
+				<0x00000038 PINMUX_SHARED_IO_Q2_3_SEL>,
+				<0x0000003c PINMUX_SHARED_IO_Q2_4_SEL>,
+				<0x00000040 PINMUX_SHARED_IO_Q2_5_SEL>,
+				<0x00000044 PINMUX_SHARED_IO_Q2_6_SEL>,
+				<0x00000048 PINMUX_SHARED_IO_Q2_7_SEL>,
+				<0x0000004c PINMUX_SHARED_IO_Q2_8_SEL>,
+				<0x00000050 PINMUX_SHARED_IO_Q2_9_SEL>,
+				<0x00000054 PINMUX_SHARED_IO_Q2_10_SEL>,
+				<0x00000058 PINMUX_SHARED_IO_Q2_11_SEL>,
+				<0x0000005c PINMUX_SHARED_IO_Q2_12_SEL>,
+				<0x00000060 PINMUX_SHARED_IO_Q3_1_SEL>,
+				<0x00000064 PINMUX_SHARED_IO_Q3_2_SEL>,
+				<0x00000068 PINMUX_SHARED_IO_Q3_3_SEL>,
+				<0x0000006c PINMUX_SHARED_IO_Q3_4_SEL>,
+				<0x00000070 PINMUX_SHARED_IO_Q3_5_SEL>,
+				<0x00000074 PINMUX_SHARED_IO_Q3_6_SEL>,
+				<0x00000078 PINMUX_SHARED_IO_Q3_7_SEL>,
+				<0x0000007c PINMUX_SHARED_IO_Q3_8_SEL>,
+				<0x00000080 PINMUX_SHARED_IO_Q3_9_SEL>,
+				<0x00000084 PINMUX_SHARED_IO_Q3_10_SEL>,
+				<0x00000088 PINMUX_SHARED_IO_Q3_11_SEL>,
+				<0x0000008c PINMUX_SHARED_IO_Q3_12_SEL>,
+				<0x00000090 PINMUX_SHARED_IO_Q4_1_SEL>,
+				<0x00000094 PINMUX_SHARED_IO_Q4_2_SEL>,
+				<0x00000098 PINMUX_SHARED_IO_Q4_3_SEL>,
+				<0x0000009c PINMUX_SHARED_IO_Q4_4_SEL>,
+				<0x000000a0 PINMUX_SHARED_IO_Q4_5_SEL>,
+				<0x000000a4 PINMUX_SHARED_IO_Q4_6_SEL>,
+				<0x000000a8 PINMUX_SHARED_IO_Q4_7_SEL>,
+				<0x000000ac PINMUX_SHARED_IO_Q4_8_SEL>,
+				<0x000000b0 PINMUX_SHARED_IO_Q4_9_SEL>,
+				<0x000000b4 PINMUX_SHARED_IO_Q4_10_SEL>,
+				<0x000000b8 PINMUX_SHARED_IO_Q4_11_SEL>,
+				<0x000000bc PINMUX_SHARED_IO_Q4_12_SEL>;
 			u-boot,dm-pre-reloc;
 		};
 
 		dedicated {
+			reg = <0xffd07200 0x00000200>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x0000000f>;
+			pinctrl-single,pins =
+				<0x0000000c PINMUX_DEDICATED_IO_4_SEL>,
+				<0x00000010 PINMUX_DEDICATED_IO_5_SEL>,
+				<0x00000014 PINMUX_DEDICATED_IO_6_SEL>,
+				<0x00000018 PINMUX_DEDICATED_IO_7_SEL>,
+				<0x0000001c PINMUX_DEDICATED_IO_8_SEL>,
+				<0x00000020 PINMUX_DEDICATED_IO_9_SEL>,
+				<0x00000024 PINMUX_DEDICATED_IO_10_SEL>,
+				<0x00000028 PINMUX_DEDICATED_IO_11_SEL>,
+				<0x0000002c PINMUX_DEDICATED_IO_12_SEL>,
+				<0x00000030 PINMUX_DEDICATED_IO_13_SEL>,
+				<0x00000034 PINMUX_DEDICATED_IO_14_SEL>,
+				<0x00000038 PINMUX_DEDICATED_IO_15_SEL>,
+				<0x0000003c PINMUX_DEDICATED_IO_16_SEL>,
+				<0x00000040 PINMUX_DEDICATED_IO_17_SEL>;
 			u-boot,dm-pre-reloc;
 		};
 
 		dedicated_cfg {
+			reg = <0xffd07200 0x00000200>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x003f3f3f>;
+			pinctrl-single,pins =
+				<0x00000100 CONFIG_IO_BANK_VSEL>,
+				<0x00000104 CONFIG_IO_MACRO (CONFIG_IO_1)>,
+				<0x00000108 CONFIG_IO_MACRO (CONFIG_IO_2)>,
+				<0x0000010c CONFIG_IO_MACRO (CONFIG_IO_3)>,
+				<0x00000110 CONFIG_IO_MACRO (CONFIG_IO_4)>,
+				<0x00000114 CONFIG_IO_MACRO (CONFIG_IO_5)>,
+				<0x00000118 CONFIG_IO_MACRO (CONFIG_IO_6)>,
+				<0x0000011c CONFIG_IO_MACRO (CONFIG_IO_7)>,
+				<0x00000120 CONFIG_IO_MACRO (CONFIG_IO_8)>,
+				<0x00000124 CONFIG_IO_MACRO (CONFIG_IO_9)>,
+				<0x00000128 CONFIG_IO_MACRO (CONFIG_IO_10)>,
+				<0x0000012c CONFIG_IO_MACRO (CONFIG_IO_11)>,
+				<0x00000130 CONFIG_IO_MACRO (CONFIG_IO_12)>,
+				<0x00000134 CONFIG_IO_MACRO (CONFIG_IO_13)>,
+				<0x00000138 CONFIG_IO_MACRO (CONFIG_IO_14)>,
+				<0x0000013c CONFIG_IO_MACRO (CONFIG_IO_15)>,
+				<0x00000140 CONFIG_IO_MACRO (CONFIG_IO_16)>,
+				<0x00000144 CONFIG_IO_MACRO (CONFIG_IO_17)>;
 			u-boot,dm-pre-reloc;
 		};
 
 		fpga {
+			reg = <0xffd07400 0x00000100>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x00000001>;
+			pinctrl-single,pins =
+				<0x00000000 PINMUX_RGMII0_USEFPGA_SEL>,
+				<0x00000004 PINMUX_RGMII1_USEFPGA_SEL>,
+				<0x00000008 PINMUX_RGMII2_USEFPGA_SEL>,
+				<0x0000000c PINMUX_I2C0_USEFPGA_SEL>,
+				<0x00000010 PINMUX_I2C1_USEFPGA_SEL>,
+				<0x00000014 PINMUX_I2CEMAC0_USEFPGA_SEL>,
+				<0x00000018 PINMUX_I2CEMAC1_USEFPGA_SEL>,
+				<0x0000001c PINMUX_I2CEMAC2_USEFPGA_SEL>,
+				<0x00000020 PINMUX_NAND_USEFPGA_SEL>,
+				<0x00000024 PINMUX_QSPI_USEFPGA_SEL>,
+				<0x00000028 PINMUX_SDMMC_USEFPGA_SEL>,
+				<0x0000002c PINMUX_SPIM0_USEFPGA_SEL>,
+				<0x00000030 PINMUX_SPIM1_USEFPGA_SEL>,
+				<0x00000034 PINMUX_SPIS0_USEFPGA_SEL>,
+				<0x00000038 PINMUX_SPIS1_USEFPGA_SEL>,
+				<0x0000003c PINMUX_UART0_USEFPGA_SEL>,
+				<0x00000040 PINMUX_UART1_USEFPGA_SEL>;
 			u-boot,dm-pre-reloc;
 		};
 	};
 
-	noc@0xffd10000 {
+	i_noc: noc@0xffd10000 {
+		compatible = "altr,socfpga-a10-noc";
+		reg = <0xffd10000 0x00008000>;
+		reg-names = "mpu_m0";
 		u-boot,dm-pre-reloc;
 
 		firewall {
+			mpu0 = <0x00000000 0x0000ffff>;
+			l3-0 = <0x00000000 0x0000ffff>;
+			fpga2sdram0-0 = <0x00000000 0x0000ffff>;
+			fpga2sdram1-0 = <0x00000000 0x0000ffff>;
+			fpga2sdram2-0 = <0x00000000 0x0000ffff>;
 			u-boot,dm-pre-reloc;
 		};
 	};
 
-	fpgabridge@0 {
+	hps_fpgabridge0: fpgabridge@0 {
+		compatible = "altr,socfpga-hps2fpga-bridge";
+		init-val = <H2F_AXI_MASTER>;
 		u-boot,dm-pre-reloc;
 	};
 
-	fpgabridge@1 {
+	hps_fpgabridge1: fpgabridge@1 {
+		compatible = "altr,socfpga-lwhps2fpga-bridge";
+		init-val = <LWH2F_AXI_MASTER>;
 		u-boot,dm-pre-reloc;
 	};
 
-	fpgabridge@2 {
+	hps_fpgabridge2: fpgabridge@2 {
+		compatible = "altr,socfpga-fpga2hps-bridge";
+		init-val = <F2H_AXI_SLAVE>;
 		u-boot,dm-pre-reloc;
 	};
 
-	fpgabridge@3 {
+	hps_fpgabridge3: fpgabridge@3 {
+		compatible = "altr,socfpga-fpga2sdram0-bridge";
+		init-val = <F2SDRAM0_AXI_SLAVE>;
 		u-boot,dm-pre-reloc;
 	};
 
-	fpgabridge@4 {
+	hps_fpgabridge4: fpgabridge@4 {
+		compatible = "altr,socfpga-fpga2sdram1-bridge";
+		init-val = <F2SDRAM1_AXI_SLAVE>;
 		u-boot,dm-pre-reloc;
 	};
 
-	fpgabridge@5 {
+	hps_fpgabridge5: fpgabridge@5 {
+		compatible = "altr,socfpga-fpga2sdram2-bridge";
+		init-val = <F2SDRAM2_AXI_SLAVE>;
 		u-boot,dm-pre-reloc;
 	};
 };
+