From patchwork Fri Oct 4 22:30:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dalon L Westergreen X-Patchwork-Id: 1172059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46lPm138wMz9sNw for ; Sat, 5 Oct 2019 08:33:21 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2C5B9C21EDC; Fri, 4 Oct 2019 22:31:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id ED173C21F1D; Fri, 4 Oct 2019 22:30:58 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B309AC21E12; Fri, 4 Oct 2019 22:30:57 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lists.denx.de (Postfix) with ESMTPS id 061E9C21E12 for ; Fri, 4 Oct 2019 22:30:56 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Oct 2019 15:30:55 -0700 X-IronPort-AV: E=Sophos;i="5.67,257,1566889200"; d="scan'208";a="217306465" Received: from dwesterg-mobl.amr.corp.intel.com (HELO dwesterg-mobl1.amr.corp.intel.com) ([10.251.26.183]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Oct 2019 15:30:54 -0700 From: Dalon Westergreen To: u-boot@lists.denx.de, tien.fong.chee@intel.com, simon.k.r.goldschmidt@gmail.com, marex@denx.de, dinguyen@kernel.org, ley.foon.tan@intel.com, chin.liang.see@intel.com Date: Fri, 4 Oct 2019 15:30:38 -0700 Message-Id: <20191004223043.18127-4-dalon.westergreen@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191004223043.18127-1-dalon.westergreen@linux.intel.com> References: <20191004223043.18127-1-dalon.westergreen@linux.intel.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Dalon Westergreen Add a common u-boot devicetree include file for the SocFPGA Arria10 device. Signed-off-by: Dalon Westergreen --- .../dts/socfpga_arria10-common-u-boot.dtsi | 206 ++++++++++++++++++ 1 file changed, 206 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10-common-u-boot.dtsi diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi new file mode 100644 index 0000000000..bd4f1271f3 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright Altera Corporation (C) 2014. All rights reserved. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + + chosen { + tick-timer = &timer2; + u-boot,dm-pre-reloc; + }; + + memory@0 { + u-boot,dm-pre-reloc; + }; + + soc { + u-boot,dm-pre-reloc; + + clkmgr@ffd04000 { + u-boot,dm-pre-reloc; + + clocks { + u-boot,dm-pre-reloc; + + cb_intosc_hs_div2_clk { + u-boot,dm-pre-reloc; + }; + + cb_intosc_ls_clk { + u-boot,dm-pre-reloc; + }; + + f2s_free_clk { + u-boot,dm-pre-reloc; + }; + + osc1 { + u-boot,dm-pre-reloc; + }; + + main_pll@40 { + u-boot,dm-pre-reloc; + + main_mpu_base_clk { + u-boot,dm-pre-reloc; + }; + + main_noc_base_clk { + u-boot,dm-pre-reloc; + }; + + main_emaca_clk@68 { + u-boot,dm-pre-reloc; + }; + + main_emacb_clk@6c { + u-boot,dm-pre-reloc; + }; + + main_emac_ptp_clk@70 { + u-boot,dm-pre-reloc; + }; + + main_gpio_db_clk@74 { + u-boot,dm-pre-reloc; + }; + + main_sdmmc_clk@78 { + u-boot,dm-pre-reloc; + }; + + main_s2f_usr0_clk@7c { + u-boot,dm-pre-reloc; + }; + + main_s2f_usr1_clk@80 { + u-boot,dm-pre-reloc; + }; + + main_hmc_pll_ref_clk@84 { + u-boot,dm-pre-reloc; + }; + + main_periph_ref_clk@9c { + u-boot,dm-pre-reloc; + }; + }; + + periph_pll@c0 { + u-boot,dm-pre-reloc; + + peri_mpu_base_clk { + u-boot,dm-pre-reloc; + }; + + peri_noc_base_clk { + u-boot,dm-pre-reloc; + }; + + peri_emaca_clk@e8 { + u-boot,dm-pre-reloc; + }; + + peri_emacb_clk@ec { + u-boot,dm-pre-reloc; + }; + + peri_emac_ptp_clk@f0 { + u-boot,dm-pre-reloc; + }; + + peri_gpio_db_clk@f4 { + u-boot,dm-pre-reloc; + }; + + peri_sdmmc_clk@f8 { + u-boot,dm-pre-reloc; + }; + + peri_s2f_usr0_clk@fc { + u-boot,dm-pre-reloc; + }; + + peri_s2f_usr1_clk@100 { + u-boot,dm-pre-reloc; + }; + + peri_hmc_pll_ref_clk@104 { + u-boot,dm-pre-reloc; + }; + }; + + mpu_free_clk@60 { + u-boot,dm-pre-reloc; + }; + + noc_free_clk@64 { + u-boot,dm-pre-reloc; + }; + + s2f_user1_free_clk@104 { + u-boot,dm-pre-reloc; + }; + + sdmmc_free_clk@f8 { + u-boot,dm-pre-reloc; + }; + + l4_sys_free_clk { + u-boot,dm-pre-reloc; + }; + + l4_main_clk { + u-boot,dm-pre-reloc; + }; + + l4_mp_clk { + u-boot,dm-pre-reloc; + }; + + l4_sp_clk { + u-boot,dm-pre-reloc; + }; + + mpu_periph_clk { + u-boot,dm-pre-reloc; + }; + + sdmmc_clk { + u-boot,dm-pre-reloc; + }; + + qspi_clk { + u-boot,dm-pre-reloc; + }; + + nand_clk { + u-boot,dm-pre-reloc; + }; + + spi_m_clk { + u-boot,dm-pre-reloc; + }; + + usb_clk { + u-boot,dm-pre-reloc; + }; + + s2f_usr1_clk { + u-boot,dm-pre-reloc; + }; + }; + }; + }; +}; + +&rst { + u-boot,dm-pre-reloc; +}; + +&timer2 { + u-boot,dm-pre-reloc; +};