diff mbox series

[U-Boot,3/8] ARM: socfpga: arria10: Add common u-boot devicetree include

Message ID 20191004223043.18127-4-dalon.westergreen@linux.intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series ARM: socfpga: arria10: Cleanup devicetree and | expand

Commit Message

Dalon L Westergreen Oct. 4, 2019, 10:30 p.m. UTC
From: Dalon Westergreen <dalon.westergreen@intel.com>

Add a common u-boot devicetree include file for the SocFPGA
Arria10 device.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
 .../dts/socfpga_arria10-common-u-boot.dtsi    | 206 ++++++++++++++++++
 1 file changed, 206 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10-common-u-boot.dtsi

Comments

Marek Vasut Oct. 4, 2019, 11:49 p.m. UTC | #1
On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> From: Dalon Westergreen <dalon.westergreen@intel.com>
> 
> Add a common u-boot devicetree include file for the SocFPGA
> Arria10 device.

Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basically
the same thing, except more fine-grained ?

> diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> new file mode 100644
> index 0000000000..bd4f1271f3
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> @@ -0,0 +1,206 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright Altera Corporation (C) 2014. All rights reserved.
> + */
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	chosen {
> +		tick-timer = &timer2;
> +		u-boot,dm-pre-reloc;
> +	};
> +
> +	memory@0 {
> +		u-boot,dm-pre-reloc;
> +	};
> +
> +	soc {
> +		u-boot,dm-pre-reloc;
> +
> +		clkmgr@ffd04000 {
> +			u-boot,dm-pre-reloc;
> +
> +			clocks {
> +					u-boot,dm-pre-reloc;
> +
> +					cb_intosc_hs_div2_clk {
> +						u-boot,dm-pre-reloc;
> +					};
> +
> +					cb_intosc_ls_clk {
> +						u-boot,dm-pre-reloc;
> +					};
> +
> +					f2s_free_clk {
> +						u-boot,dm-pre-reloc;
> +					};
> +
> +					osc1 {
> +						u-boot,dm-pre-reloc;
> +					};
> +
> +					main_pll@40 {
> +						u-boot,dm-pre-reloc;
> +
> +						main_mpu_base_clk {
> +							u-boot,dm-pre-reloc;
> +						};
> +
> +						main_noc_base_clk {
> +							u-boot,dm-pre-reloc;
> +						};
> +
> +						main_emaca_clk@68 {
> +							u-boot,dm-pre-reloc;
> +						};

Do we really need all this in SPL for every board ?
Dalon L Westergreen Oct. 5, 2019, 11:25 p.m. UTC | #2
On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <dalon.westergreen@intel.com>
> > Add a common u-boot devicetree include file for the SocFPGAArria10 device.
> 
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
> thing, except more fine-grained ?
> > diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsinew file mode 100644index
> > 0000000000..bd4f1271f3--- /dev/null+++ b/arch/arm/dts/socfpga_arria10-
> > common-u-boot.dtsi@@ -0,0 +1,206 @@+// SPDX-License-Identifier: GPL-2.0+/*+
> > * Copyright Altera Corporation (C) 2014. All rights reserved.+ */++/ {+	
> > #address-cells = <1>;+	#size-cells = <1>;++	chosen {+		tick
> > -timer = &timer2;+		u-boot,dm-pre-reloc;+	};++	memory@0 {+	
> > 	u-boot,dm-pre-reloc;+	};++	soc {+		u-boot,dm-pre-
> > reloc;++		clkmgr@ffd04000 {+			u-boot,dm-pre-
> > reloc;++			clocks {+					u-
> > boot,dm-pre-reloc;++					cb_intosc_hs_div
> > 2_clk {+						u-boot,dm-pre-reloc;+	
> > 				};++					cb_i
> > ntosc_ls_clk {+						u-boot,dm-pre-
> > reloc;+					};++				
> > 	f2s_free_clk {+						u-boot,dm-
> > pre-reloc;+					};++				
> > 	osc1 {+						u-boot,dm-pre-
> > reloc;+					};++				
> > 	main_pll@40 {+						u-boot,dm-
> > pre-reloc;++						main_mpu_base_cl
> > k {+							u-boot,dm-pre-
> > reloc;+						};++			
> > 			main_noc_base_clk {+					
> > 		u-boot,dm-pre-reloc;+						
> > };++						main_emaca_clk@68 {+	
> > 						u-boot,dm-pre-reloc;+		
> > 				};
> 
> Do we really need all this in SPL for every board ?

We likely don't, but we arent that memory constrained in a10 and this simplifies
devicetree creation for custom boards.  We do have customers using ethernet
in spl, for example.  I can slim this down, but is it necessary?

--dalon
Marek Vasut Oct. 6, 2019, 1:40 p.m. UTC | #3
On 10/6/19 1:25 AM, Dalon L Westergreen wrote:
> On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
>> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>>> From: Dalon Westergreen <dalon.westergreen@intel.com>
>>> Add a common u-boot devicetree include file for the SocFPGAArria10 device.
>>
>> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
>> thing, except more fine-grained ?
>>> diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
>>> b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsinew file mode 100644index
>>> 0000000000..bd4f1271f3--- /dev/null+++ b/arch/arm/dts/socfpga_arria10-
>>> common-u-boot.dtsi@@ -0,0 +1,206 @@+// SPDX-License-Identifier: GPL-2.0+/*+
>>> * Copyright Altera Corporation (C) 2014. All rights reserved.+ */++/ {+	
>>> #address-cells = <1>;+	#size-cells = <1>;++	chosen {+		tick
>>> -timer = &timer2;+		u-boot,dm-pre-reloc;+	};++	memory@0 {+	
>>> 	u-boot,dm-pre-reloc;+	};++	soc {+		u-boot,dm-pre-
>>> reloc;++		clkmgr@ffd04000 {+			u-boot,dm-pre-
>>> reloc;++			clocks {+					u-
>>> boot,dm-pre-reloc;++					cb_intosc_hs_div
>>> 2_clk {+						u-boot,dm-pre-reloc;+	
>>> 				};++					cb_i
>>> ntosc_ls_clk {+						u-boot,dm-pre-
>>> reloc;+					};++				
>>> 	f2s_free_clk {+						u-boot,dm-
>>> pre-reloc;+					};++				
>>> 	osc1 {+						u-boot,dm-pre-
>>> reloc;+					};++				
>>> 	main_pll@40 {+						u-boot,dm-
>>> pre-reloc;++						main_mpu_base_cl
>>> k {+							u-boot,dm-pre-
>>> reloc;+						};++			
>>> 			main_noc_base_clk {+					
>>> 		u-boot,dm-pre-reloc;+						
>>> };++						main_emaca_clk@68 {+	
>>> 						u-boot,dm-pre-reloc;+		
>>> 				};
>>
>> Do we really need all this in SPL for every board ?
> 
> We likely don't, but we arent that memory constrained in a10 and this simplifies
> devicetree creation for custom boards.

We shouldn't enable what we don't need in SPL.

> We do have customers using ethernet
> in spl, for example.  I can slim this down, but is it necessary?

Just enable the necessary clock in the board-specific DT, since it's a
board-specific configuration.
Dalon L Westergreen Oct. 7, 2019, 3:30 a.m. UTC | #4
On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <dalon.westergreen@intel.com>
> > Add a common u-boot devicetree include file for the SocFPGAArria10 device.
> 
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
> thing, except more fine-grained ?

I wanted to keep the dts fragment dependent on the handoff header separate from
thegeneric base u-boot include.
> > diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsinew file mode 100644index
> > 0000000000..bd4f1271f3--- /dev/null+++ b/arch/arm/dts/socfpga_arria10-
> > common-u-boot.dtsi@@ -0,0 +1,206 @@+// SPDX-License-Identifier: GPL-2.0+/*+
> > * Copyright Altera Corporation (C) 2014. All rights reserved.+ */++/ {+	
> > #address-cells = <1>;+	#size-cells = <1>;++	chosen {+		tick
> > -timer = &timer2;+		u-boot,dm-pre-reloc;+	};++	memory@0 {+	
> > 	u-boot,dm-pre-reloc;+	};++	soc {+		u-boot,dm-pre-
> > reloc;++		clkmgr@ffd04000 {+			u-boot,dm-pre-
> > reloc;++			clocks {+					u-
> > boot,dm-pre-reloc;++					cb_intosc_hs_div
> > 2_clk {+						u-boot,dm-pre-reloc;+	
> > 				};++					cb_i
> > ntosc_ls_clk {+						u-boot,dm-pre-
> > reloc;+					};++				
> > 	f2s_free_clk {+						u-boot,dm-
> > pre-reloc;+					};++				
> > 	osc1 {+						u-boot,dm-pre-
> > reloc;+					};++				
> > 	main_pll@40 {+						u-boot,dm-
> > pre-reloc;++						main_mpu_base_cl
> > k {+							u-boot,dm-pre-
> > reloc;+						};++			
> > 			main_noc_base_clk {+					
> > 		u-boot,dm-pre-reloc;+						
> > };++						main_emaca_clk@68 {+	
> > 						u-boot,dm-pre-reloc;+		
> > 				};
> 
> Do we really need all this in SPL for every board ?
Simon Goldschmidt Oct. 7, 2019, 2:04 p.m. UTC | #5
On Mon, Oct 7, 2019 at 3:38 PM Dalon L Westergreen
<dalon.westergreen@linux.intel.com> wrote:
>
> On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
>
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>
> From: Dalon Westergreen <
>
> dalon.westergreen@intel.com
>
> >
>
>
> Add a common u-boot devicetree include file for the SocFPGA
>
> Arria10 device.
>
>
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basically
>
> the same thing, except more fine-grained ?
>
>
> I wanted to keep the dts fragment dependent on the handoff header separate from the
> generic base u-boot include.

Hmm, ok, I see. Is it encouraged to add more header files in arch/arm/dts?
If so, I wouldn't be too opposed on going that way for gen5 as well...

Regards,
Simon

>
>
> diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
>
> new file mode 100644
>
> index 0000000000..bd4f1271f3
>
> --- /dev/null
>
> +++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
>
> @@ -0,0 +1,206 @@
>
> +// SPDX-License-Identifier: GPL-2.0
>
> +/*
>
> + * Copyright Altera Corporation (C) 2014. All rights reserved.
>
> + */
>
> +
>
> +/ {
>
> + #address-cells = <1>;
>
> + #size-cells = <1>;
>
> +
>
> + chosen {
>
> + tick-timer = &timer2;
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + memory@0 {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + soc {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + clkmgr@ffd04000 {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + clocks {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + cb_intosc_hs_div2_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + cb_intosc_ls_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + f2s_free_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + osc1 {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + main_pll@40 {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + main_mpu_base_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + main_noc_base_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + main_emaca_clk@68 {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
>
> Do we really need all this in SPL for every board ?
diff mbox series

Patch

diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
new file mode 100644
index 0000000000..bd4f1271f3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
@@ -0,0 +1,206 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		tick-timer = &timer2;
+		u-boot,dm-pre-reloc;
+	};
+
+	memory@0 {
+		u-boot,dm-pre-reloc;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+
+		clkmgr@ffd04000 {
+			u-boot,dm-pre-reloc;
+
+			clocks {
+					u-boot,dm-pre-reloc;
+
+					cb_intosc_hs_div2_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					cb_intosc_ls_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					f2s_free_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					osc1 {
+						u-boot,dm-pre-reloc;
+					};
+
+					main_pll@40 {
+						u-boot,dm-pre-reloc;
+
+						main_mpu_base_clk {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_noc_base_clk {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_emaca_clk@68 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_emacb_clk@6c {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_emac_ptp_clk@70 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_gpio_db_clk@74 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_sdmmc_clk@78 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_s2f_usr0_clk@7c {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_s2f_usr1_clk@80 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_hmc_pll_ref_clk@84 {
+							u-boot,dm-pre-reloc;
+						};
+
+						main_periph_ref_clk@9c {
+							u-boot,dm-pre-reloc;
+						};
+					};
+
+					periph_pll@c0 {
+						u-boot,dm-pre-reloc;
+
+						peri_mpu_base_clk {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_noc_base_clk {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_emaca_clk@e8 {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_emacb_clk@ec {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_emac_ptp_clk@f0 {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_gpio_db_clk@f4 {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_sdmmc_clk@f8 {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_s2f_usr0_clk@fc {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_s2f_usr1_clk@100 {
+							u-boot,dm-pre-reloc;
+						};
+
+						peri_hmc_pll_ref_clk@104 {
+							u-boot,dm-pre-reloc;
+						};
+					};
+
+					mpu_free_clk@60 {
+						u-boot,dm-pre-reloc;
+					};
+
+					noc_free_clk@64 {
+						u-boot,dm-pre-reloc;
+					};
+
+					s2f_user1_free_clk@104 {
+						u-boot,dm-pre-reloc;
+					};
+
+					sdmmc_free_clk@f8 {
+						u-boot,dm-pre-reloc;
+					};
+
+					l4_sys_free_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					l4_main_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					l4_mp_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					l4_sp_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					mpu_periph_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					sdmmc_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					qspi_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					nand_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					spi_m_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					usb_clk {
+						u-boot,dm-pre-reloc;
+					};
+
+					s2f_usr1_clk {
+						u-boot,dm-pre-reloc;
+					};
+				};
+		};
+	};
+};
+
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&timer2 {
+	u-boot,dm-pre-reloc;
+};