From patchwork Tue Oct 1 11:56:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 1169862 X-Patchwork-Delegate: lukma@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="W+dqFRxn"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46jHqH6z3Qz9sN1 for ; Tue, 1 Oct 2019 21:58:51 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A6A37C21C4A; Tue, 1 Oct 2019 11:58:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 94C10C21DE8; Tue, 1 Oct 2019 11:58:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AB71EC21C57; Tue, 1 Oct 2019 11:56:47 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lists.denx.de (Postfix) with ESMTPS id CF36BC21C93 for ; Tue, 1 Oct 2019 11:56:44 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x91Buf4b101483; Tue, 1 Oct 2019 06:56:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569931001; bh=WqBr9szUsybKx6NI897myfKb2YtJyDNjXf4kUVq2vq4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=W+dqFRxnmgFf5VwfH2ZT1h4MeUg5xoOMrm0h3uF7qNXWLdEzhGk9hC3DFm8rhgXLG oD+G8uLc1/0HrGzOeDlFMu4n6YYJfFbE4MrG0FC3Yz15T7/1YdAVV6oI35W3oI2WTE XTuAwMgrwEQ0ziEHknbGWGbfsqlBdmWu05q4TQVg= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x91BufcR076049 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Oct 2019 06:56:41 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 1 Oct 2019 06:56:30 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 1 Oct 2019 06:56:39 -0500 Received: from a0132425.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x91BuF0n019461; Tue, 1 Oct 2019 06:56:37 -0500 From: Vignesh Raghavendra To: Marek Vasut , Lukasz Majewski Date: Tue, 1 Oct 2019 17:26:35 +0530 Message-ID: <20191001115636.21052-8-vigneshr@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191001115636.21052-1-vigneshr@ti.com> References: <20191001115636.21052-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 7/8] usb: cdns3: Add TI wrapper driver for CDNS USB3 controller X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add driver to handle TI specific wrapper for Cadence USB3 controller present on J721e SoC. Based on Linux driver for the same. Signed-off-by: Vignesh Raghavendra --- drivers/usb/cdns3/Kconfig | 7 ++ drivers/usb/cdns3/Makefile | 2 + drivers/usb/cdns3/cdns3-ti.c | 193 +++++++++++++++++++++++++++++++++++ 3 files changed, 202 insertions(+) create mode 100644 drivers/usb/cdns3/cdns3-ti.c diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig index 25c0f103e742..4cf59c70d431 100644 --- a/drivers/usb/cdns3/Kconfig +++ b/drivers/usb/cdns3/Kconfig @@ -48,4 +48,11 @@ config SPL_USB_CDNS3_HOST Host controller is compliant with XHCI so it will use standard XHCI driver. + +config USB_CDNS3_TI + tristate "Cadence USB3 support on TI platforms" + default USB_CDNS3 + help + Say 'Y' here if you are building for Texas Instruments + platforms that contain Cadence USB3 controller core. E.g.: J721e. endif diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile index 525477954dd8..18d7190755d2 100644 --- a/drivers/usb/cdns3/Makefile +++ b/drivers/usb/cdns3/Makefile @@ -7,3 +7,5 @@ obj-$(CONFIG_USB_CDNS3) += cdns3.o cdns3-$(CONFIG_$(SPL_)USB_CDNS3_GADGET) += gadget.o ep0.o cdns3-$(CONFIG_$(SPL_)USB_CDNS3_HOST) += host.o + +obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c new file mode 100644 index 000000000000..2fa0104f1bee --- /dev/null +++ b/drivers/usb/cdns3/cdns3-ti.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * cdns_ti-ti.c - TI specific Glue layer for Cadence USB Controller + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" + +/* USB Wrapper register offsets */ +#define USBSS_PID 0x0 +#define USBSS_W1 0x4 +#define USBSS_STATIC_CONFIG 0x8 +#define USBSS_PHY_TEST 0xc +#define USBSS_DEBUG_CTRL 0x10 +#define USBSS_DEBUG_INFO 0x14 +#define USBSS_DEBUG_LINK_STATE 0x18 +#define USBSS_DEVICE_CTRL 0x1c + +/* Wrapper 1 register bits */ +#define USBSS_W1_PWRUP_RST BIT(0) +#define USBSS_W1_OVERCURRENT_SEL BIT(8) +#define USBSS_W1_MODESTRAP_SEL BIT(9) +#define USBSS_W1_OVERCURRENT BIT(16) +#define USBSS_W1_MODESTRAP_MASK GENMASK(18, 17) +#define USBSS_W1_MODESTRAP_SHIFT 17 +#define USBSS_W1_USB2_ONLY BIT(19) + +/* Static config register bits */ +#define USBSS1_STATIC_PLL_REF_SEL_MASK GENMASK(8, 5) +#define USBSS1_STATIC_PLL_REF_SEL_SHIFT 5 +#define USBSS1_STATIC_LOOPBACK_MODE_MASK GENMASK(4, 3) +#define USBSS1_STATIC_LOOPBACK_MODE_SHIFT 3 +#define USBSS1_STATIC_VBUS_SEL_MASK GENMASK(2, 1) +#define USBSS1_STATIC_VBUS_SEL_SHIFT 1 +#define USBSS1_STATIC_LANE_REVERSE BIT(0) + +/* Modestrap modes */ +enum modestrap_mode { USBSS_MODESTRAP_MODE_NONE, + USBSS_MODESTRAP_MODE_HOST, + USBSS_MODESTRAP_MODE_PERIPHERAL}; + +struct cdns_ti { + struct udevice *dev; + void __iomem *usbss; + int usb2_only:1; + int vbus_divider:1; + struct clk *usb2_refclk; + struct clk *lpm_clk; +}; + +static const int cdns_ti_rate_table[] = { /* in KHZ */ + 9600, + 10000, + 12000, + 19200, + 20000, + 24000, + 25000, + 26000, + 38400, + 40000, + 58000, + 50000, + 52000, +}; + +static inline u32 cdns_ti_readl(struct cdns_ti *data, u32 offset) +{ + return readl(data->usbss + offset); +} + +static inline void cdns_ti_writel(struct cdns_ti *data, u32 offset, u32 value) +{ + writel(value, data->usbss + offset); +} + +static int cdns_ti_probe(struct udevice *dev) +{ + struct cdns_ti *data = dev_get_platdata(dev); + struct clk usb2_refclk; + int modestrap_mode; + unsigned long rate; + int rate_code, i; + u32 reg; + int ret; + + data->dev = dev; + + data->usbss = dev_remap_addr_index(dev, 0); + if (!data->usbss) + return -EINVAL; + + ret = clk_get_by_name(dev, "usb2_refclk", &usb2_refclk); + if (ret) { + dev_err(dev, "Failed to get usb2_refclk\n"); + return ret; + } + + rate = clk_get_rate(&usb2_refclk); + rate /= 1000; /* To KHz */ + for (i = 0; i < ARRAY_SIZE(cdns_ti_rate_table); i++) { + if (cdns_ti_rate_table[i] == rate) + break; + } + + if (i == ARRAY_SIZE(cdns_ti_rate_table)) { + dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate); + return -EINVAL; + } + + rate_code = i; + + /* assert RESET */ + reg = cdns_ti_readl(data, USBSS_W1); + reg &= ~USBSS_W1_PWRUP_RST; + cdns_ti_writel(data, USBSS_W1, reg); + + /* set static config */ + reg = cdns_ti_readl(data, USBSS_STATIC_CONFIG); + reg &= ~USBSS1_STATIC_PLL_REF_SEL_MASK; + reg |= rate_code << USBSS1_STATIC_PLL_REF_SEL_SHIFT; + + reg &= ~USBSS1_STATIC_VBUS_SEL_MASK; + data->vbus_divider = dev_read_bool(dev, "ti,vbus-divider"); + if (data->vbus_divider) + reg |= 1 << USBSS1_STATIC_VBUS_SEL_SHIFT; + + cdns_ti_writel(data, USBSS_STATIC_CONFIG, reg); + reg = cdns_ti_readl(data, USBSS_STATIC_CONFIG); + + /* set USB2_ONLY mode if requested */ + reg = cdns_ti_readl(data, USBSS_W1); + data->usb2_only = dev_read_bool(dev, "ti,usb2-only"); + if (data->usb2_only) + reg |= USBSS_W1_USB2_ONLY; + + /* set modestrap */ + if (dev_read_bool(dev, "ti,modestrap-host")) + modestrap_mode = USBSS_MODESTRAP_MODE_HOST; + else if (dev_read_bool(dev, "ti,modestrap-peripheral")) + modestrap_mode = USBSS_MODESTRAP_MODE_PERIPHERAL; + else + modestrap_mode = USBSS_MODESTRAP_MODE_NONE; + + reg |= USBSS_W1_MODESTRAP_SEL; + reg &= ~USBSS_W1_MODESTRAP_MASK; + reg |= modestrap_mode << USBSS_W1_MODESTRAP_SHIFT; + cdns_ti_writel(data, USBSS_W1, reg); + + /* de-assert RESET */ + reg |= USBSS_W1_PWRUP_RST; + cdns_ti_writel(data, USBSS_W1, reg); + + return 0; +} + +static int cdns_ti_remove(struct udevice *dev) +{ + struct cdns_ti *data = dev_get_platdata(dev); + u32 reg; + + /* put device back to RESET*/ + reg = cdns_ti_readl(data, USBSS_W1); + reg &= ~USBSS_W1_PWRUP_RST; + cdns_ti_writel(data, USBSS_W1, reg); + + return 0; +} + +static const struct udevice_id cdns_ti_of_match[] = { + { .compatible = "ti,j721e-usb", }, + {}, +}; + +U_BOOT_DRIVER(cdns_ti) = { + .name = "cdns-ti", + .id = UCLASS_NOP, + .of_match = cdns_ti_of_match, + .bind = cdns3_bind, + .probe = cdns_ti_probe, + .remove = cdns_ti_remove, + .platdata_auto_alloc_size = sizeof(struct cdns_ti), + .flags = DM_FLAG_OS_PREPARE, +};