From patchwork Fri Sep 27 08:02:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1168331 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="xT1++2Q+"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46fkqZ5bs6z9sPY for ; Fri, 27 Sep 2019 18:05:14 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 822DAC21C29; Fri, 27 Sep 2019 08:03:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 08AC7C21D65; Fri, 27 Sep 2019 08:03:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 882FDC21E29; Fri, 27 Sep 2019 08:03:13 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id 5CEB9C21C29 for ; Fri, 27 Sep 2019 08:03:12 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8R83AuP067886; Fri, 27 Sep 2019 03:03:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569571390; bh=AeRIvOn31i4HpRXxri6tBrQxGASp0xTss2o0bwZklcA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xT1++2Q+oTiz5sdHw5nqPd35s8vh7mD7EZbjmFloD6+S8FF3yK/bCeUBb/ieMl2jL i46GK9kWaHBDUQKRsdY72DKz1yZdzUhtZpMEuStlVMk/R2W7d2txCclqEHskLBFCCa Kpu+KfJ7XqqkcKpgfVpeN53MvruJ++EyN1Y3CuCU= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8R83Auf032591 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 27 Sep 2019 03:03:10 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 27 Sep 2019 03:03:09 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 27 Sep 2019 03:03:02 -0500 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8R835JD004459; Fri, 27 Sep 2019 03:03:08 -0500 From: Lokesh Vutla To: Tom Rini , Date: Fri, 27 Sep 2019 13:32:11 +0530 Message-ID: <20190927080215.2084-2-lokeshvutla@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190927080215.2084-1-lokeshvutla@ti.com> References: <20190927080215.2084-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH v2 1/5] arm: k3: Add support for printing CPUINFO X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add support for printing CPU info for all K3 devices. Signed-off-by: Lokesh Vutla --- arch/arm/mach-k3/common.c | 42 ++++++++++++++++++++++++ arch/arm/mach-k3/common.h | 6 ++++ arch/arm/mach-k3/include/mach/hardware.h | 18 ++++++++++ 3 files changed, 66 insertions(+) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 3e36d90ace..2b6c7d237e 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include struct ti_sci_handle *get_ti_sci_handle(void) { @@ -144,3 +146,43 @@ void reset_cpu(ulong ignored) { } #endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + u32 soc, rev; + char *name; + + soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) & + DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT; + rev = (readl(CTRLMMR_WKUP_JTAG_ID) & + JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT; + + printf("SoC: "); + switch (soc) { + case AM654: + name = "AM654"; + break; + case J721E: + name = "J721E"; + break; + default: + name = "Unknown Silicon"; + }; + + printf("%s PG ", name); + switch (rev) { + case REV_PG1_0: + name = "1.0"; + break; + case REV_PG2_0: + name = "2.0"; + break; + default: + name = "Unknown Revision"; + }; + printf("%s\n", name); + + return 0; +} +#endif diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index ac7e80d9af..1db253c8c6 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -8,4 +8,10 @@ #include +#define AM654 2 +#define J721E 4 + +#define REV_PG1_0 0 +#define REV_PG2_0 1 + void setup_k3_mpu_regions(void); diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 4e629822aa..d670d5a56e 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -13,4 +13,22 @@ #ifdef CONFIG_SOC_K3_J721E #include "j721e_hardware.h" #endif + +/* Assuming these addresses and definitions stay common across K3 devices */ +#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018 +#define DEVICE_ID_FAMILY_SHIFT 26 +#define DEVICE_ID_FAMILY_MASK (0x3f << 26) +#define DEVICE_ID_BASE_SHIFT 11 +#define DEVICE_ID_BASE_MASK (0x1fff << 11) +#define DEVICE_ID_SPEED_SHIFT 6 +#define DEVICE_ID_SPEED_MASK (0x1f << 6) +#define DEVICE_ID_TEMP_SHIFT 3 +#define DEVICE_ID_TEMP_MASK (0x7 << 3) + +#define CTRLMMR_WKUP_JTAG_ID 0x43000014 +#define JTAG_ID_VARIANT_SHIFT 28 +#define JTAG_ID_VARIANT_MASK (0xf << 28) +#define JTAG_ID_PARTNO_SHIFT 12 +#define JTAG_ID_PARTNO_MASK (0x7ff << 1) + #endif /* _ASM_ARCH_HARDWARE_H_ */