| Message ID | 20190927044329.21145-4-vigneshr@ti.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | spi-nor: spi-nor-ids: Fix 4 Byte addressing | expand |
On 09/27/2019 07:43 AM, Vignesh Raghavendra wrote: > External E-Mail > > > mt25qu512a flash has Flag status register that indicates various errors > that may be encountered during erase/write operations. Therefore add > USE_FSR flag to the entry > n25q256 & 512 support flag status register command. Would you add the flag for them too? mtq256 probably too. > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> anyway, looks good: Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > drivers/mtd/spi/spi-nor-ids.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c > index c7b6cf002c54..2e0aebbc44aa 100644 > --- a/drivers/mtd/spi/spi-nor-ids.c > +++ b/drivers/mtd/spi/spi-nor-ids.c > @@ -166,7 +166,8 @@ const struct flash_info spi_nor_ids[] = { > { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, > - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | > + USE_FSR) }, > { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, >
On Tue, Oct 1, 2019 at 7:23 AM <Tudor.Ambarus@microchip.com> wrote: > > > > On 09/27/2019 07:43 AM, Vignesh Raghavendra wrote: > > External E-Mail > > > > > > mt25qu512a flash has Flag status register that indicates various errors > > that may be encountered during erase/write operations. Therefore add > > USE_FSR flag to the entry > > > n25q256 & 512 support flag status register command. Would you add the flag for > them too? mtq256 probably too. Right, the datasheet of my mt25q says flag status register command is supported. Otherwise: Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Regards, Simon > > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > > anyway, looks good: > Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> > > > --- > > drivers/mtd/spi/spi-nor-ids.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c > > index c7b6cf002c54..2e0aebbc44aa 100644 > > --- a/drivers/mtd/spi/spi-nor-ids.c > > +++ b/drivers/mtd/spi/spi-nor-ids.c > > @@ -166,7 +166,8 @@ const struct flash_info spi_nor_ids[] = { > > { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > > { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > > { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, > > - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > > + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | > > + USE_FSR) }, > > { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > > { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > > { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > >
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index c7b6cf002c54..2e0aebbc44aa 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -166,7 +166,8 @@ const struct flash_info spi_nor_ids[] = { { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_FSR) }, { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
mt25qu512a flash has Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag to the entry Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> --- drivers/mtd/spi/spi-nor-ids.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)