From patchwork Wed Sep 25 15:00:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1167537 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="bvdpseuy"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46dl2P0sNWz9sPK for ; Thu, 26 Sep 2019 03:11:08 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id AFE31C21F99; Wed, 25 Sep 2019 17:09:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E5966C222A1; Wed, 25 Sep 2019 15:08:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E21CBC22294; Wed, 25 Sep 2019 15:07:49 +0000 (UTC) Received: from mail-io1-f45.google.com (mail-io1-f45.google.com [209.85.166.45]) by lists.denx.de (Postfix) with ESMTPS id ABAA3C22090 for ; Wed, 25 Sep 2019 15:02:55 +0000 (UTC) Received: by mail-io1-f45.google.com with SMTP id c25so14622021iot.12 for ; Wed, 25 Sep 2019 08:02:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W+VSFioqds0jL8xuds/gLoGKmUn4m+7EwvnzqVBPILw=; b=bvdpseuytEjrn7Y/wYcVOXycppGaopdasuBymhtOoqG/2/ONc4yFiMtPgWLktR6/Kn vAEN3x1KpeJSzeyXlbLImN3ncyA4MXT05l2SDl3RMJq9UgO789qbmvA2fl81YQ/4hnzQ u5JAg7go67gtRq3QFrQGrLyL/PwU4btj3BFJc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W+VSFioqds0jL8xuds/gLoGKmUn4m+7EwvnzqVBPILw=; b=DfSj0yf9CpDeCi4Y+g1cIGoNYpvBUK12QS/bXTyqgrT8bmsnsOAFrQ3ZFmjVl9h2+N cRnVJWz5SoGjjDVFTniaG3vXX+3ZG5CVFwN3KhWGR5a8NuECF+X8UP9aRGi2gzhPaizx r2bpfH3OGfxQvlqRbxY0sxOW2f9rawlR8Oqbx/w3CVxDtN+4A0Ok2PsnhKrTYJToVgqw Ms/efapY3/8hEpAZE2T14B+z9p4/x98rNgddmEItyIT+2MaP5SC5PH37WKhfhmG6tgE+ ahFTO/+rrR68F/BFWCYfQuILX+/LeuCexYrAmgz6W+liLBd+9/b6RVgU3tuHwwQfYm6V cXbA== X-Gm-Message-State: APjAAAUHkSiVyykRYe3wuKgEFa55vD12nrxGJW5m5SHD0iwEjcr+rovM IMefkrR5x5Q8gex7Zea4yny96CTi3FE= X-Google-Smtp-Source: APXvYqzDLZ0k4NUPjrEDAzm0cwm1Zi3XwsT0YUzVSW2CTwouD3DQEtPzPTGWrEv4kOearmttUiyI1g== X-Received: by 2002:a92:8454:: with SMTP id l81mr850905ild.20.1569423773979; Wed, 25 Sep 2019 08:02:53 -0700 (PDT) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id 197sm6758613ioc.78.2019.09.25.08.02.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 08:02:53 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Wed, 25 Sep 2019 09:00:51 -0600 Message-Id: <20190925150052.201698-126-sjg@chromium.org> X-Mailer: git-send-email 2.23.0.444.g18eeb5a265-goog In-Reply-To: <20190925150052.201698-102-sjg@chromium.org> References: <20190925150052.201698-102-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH 125/126] x86: Add chromebook_coral X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add support for coral which is a range of apollolake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by: Simon Glass --- arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_coral.dts | 298 ++++++++++++++++++++++ board/google/Kconfig | 15 ++ board/google/chromebook_coral/Kconfig | 43 ++++ board/google/chromebook_coral/MAINTAINERS | 6 + board/google/chromebook_coral/Makefile | 5 + board/google/chromebook_coral/coral.c | 18 ++ configs/chromebook_coral_defconfig | 95 +++++++ doc/board/google/chromebook_coral.rst | 25 ++ include/configs/chromebook_coral.h | 29 +++ 10 files changed, 535 insertions(+) create mode 100644 arch/x86/dts/chromebook_coral.dts create mode 100644 board/google/chromebook_coral/Kconfig create mode 100644 board/google/chromebook_coral/MAINTAINERS create mode 100644 board/google/chromebook_coral/Makefile create mode 100644 board/google/chromebook_coral/coral.c create mode 100644 configs/chromebook_coral_defconfig create mode 100644 doc/board/google/chromebook_coral.rst create mode 100644 include/configs/chromebook_coral.h diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index d4bdf62be6d..be209aaaf8f 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -2,6 +2,7 @@ dtb-y += bayleybay.dtb \ cherryhill.dtb \ + chromebook_coral.dtb \ chromebook_link.dtb \ chromebox_panther.dtb \ chromebook_samus.dtb \ diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts new file mode 100644 index 00000000000..8f50ce2f94d --- /dev/null +++ b/arch/x86/dts/chromebook_coral.dts @@ -0,0 +1,298 @@ +/dts-v1/; + +#include + +/include/ "skeleton.dtsi" +/include/ "keyboard.dtsi" +/include/ "reset.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +#ifdef CONFIG_CHROMEOS +#include "chromeos-x86.dtsi" +#include "flashmap-x86-ro.dtsi" +#include "flashmap-16mb-rw.dtsi" +#endif + +#include +#include +#include +#include + +/ { + model = "Google Coral"; + compatible = "google,coral", "intel,apollolake"; + + aliases { + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = &serial; + }; + + cpus { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <1>; + intel,apic-id = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <2>; + intel,apic-id = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <3>; + intel,apic-id = <3>; + }; + + }; + + keyboard { + intel,duplicate-por; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xe0000000 0 0x10000000 + 0x42000000 0x0 0xb0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x1000 0x1000 0 0xefff>; + + host_bridge: host-bridge@0,0 { + u-boot,dm-pre-reloc; + reg = <0x00000000 0 0 0 0>; + compatible = "intel,apl-hostbridge"; + pciex-region-size = <0x10000000>; + }; + + punit@0,1 { + u-boot,dm-pre-reloc; + reg = <0x00000800 0 0 0 0>; + compatible = "intel,apl-punit"; + }; + + p2sb: p2sb@d,0 { + u-boot,dm-pre-reloc; + reg = <0x02006810 0 0 0 0>; + compatible = "intel,apl-p2sb"; + early-regs = ; + + gpio_n: n { + compatible = "intel,apl-gpio"; + intel,p2sb-port-id = ; + }; + + nw { + u-boot,dm-pre-reloc; + compatible = "intel,apl-gpio"; + intel,p2sb-port-id = ; + }; + + w { + u-boot,dm-pre-reloc; + compatible = "intel,apl-gpio"; + intel,p2sb-port-id = ; + }; + + sw { + compatible = "intel,apl-gpio"; + intel,p2sb-port-id = ; + }; + + itss { + u-boot,dm-pre-reloc; + compatible = "intel,apl-itss"; + intel,p2sb-port-id = ; + intel,pmc-routes = < + PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0 + PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32 + PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0 + PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32 + PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64 + PMC_GPE_N_31_0 GPIO_GPE_N_31_0 + PMC_GPE_N_63_32 GPIO_GPE_N_63_32 + PMC_GPE_W_31_0 GPIO_GPE_W_31_0>; + }; + }; + + pmc@d,1 { + u-boot,dm-pre-reloc; + reg = <0x6900 0 0 0 0>; + + /* + * Values for BAR0, BAR2 and ACPI_BASE for when PCI + * auto-configure is not available + */ + early-regs = <0xfe042000 0x2000 + 0xfe044000 0x2000 + 0x400 0x100>; + compatible = "intel,apl-pmc"; + gpe0-dwx-mask = <0xf>; + gpe0-dwx-shift-base = <4>; + gpe0-dw = ; + gpe0-sts = <0x20>; + gpe0-en = <0x30>; + }; + + fast-spi@d,2 { + u-boot,dm-pre-reloc; + reg = <0x02006a10 0 0 0 0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "intel,fast-spi"; + early-regs = ; + memory-map = <0xff800000 0x00800000>; + + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x003e0000 0x00010000>; + u-boot,dm-pre-reloc; + }; + rw-var-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x003f0000 0x0001000>; + u-boot,dm-pre-reloc; + }; + + }; + + serial: serial@18,2 { + reg = <0x0200c210 0 0 0 0>; + u-boot,dm-pre-reloc; + compatible = "intel,apl-ns16550"; + early-regs = <0xde000000 0x20>; + reg-shift = <2>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + pch: pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,apl-pch"; + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + + lpc { + compatible = "intel,apl-lpc"; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + }; + }; + }; + +}; + +&gpio_n { + u-boot,dm-pre-reloc; + early-pads = < + /* These two are for the debug UART */ + GPIO_46 /* UART2 RX */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TxLASTRxE) + + GPIO_47 /* UART2 TX */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TxLASTRxE) + + GPIO_75 /* I2S1_BCLK -- PCH_WP */ + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TxDRxE) + + /* I2C2 - TPM */ + GPIO_128 /* LPSS_I2C2_SDA */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TxLASTRxE) + GPIO_129 /* LPSS_I2C2_SCL */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TxLASTRxE) + GPIO_28 /* TPM IRQ */ + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP | + PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT) + (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TxDRxE) + + /* + * WLAN_PE_RST - default to deasserted just in case FSP + * misbehaves + */ + GPIO_122 /* SIO_SPI_2_RXD */ + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP | + PAD_CFG0_RX_DISABLE | 0) + (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TxLASTRxE) + >; +}; + +&host_bridge { + lpddr4-swizzle = /bits/ 8 < + /* LP4_PHYS_CH0A */ + + /* DQA[0:7] pins of LPDDR4 module */ + 6 7 5 4 3 1 0 2 + /* DQA[8:15] pins of LPDDR4 module */ + 12 10 11 13 14 8 9 15 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 16 22 23 20 18 17 19 21 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 30 28 29 25 24 26 27 31 + + /* LP4_PHYS_CH0B */ + /* DQA[0:7] pins of LPDDR4 module */ + 7 3 5 2 6 0 1 4 + /* DQA[8:15] pins of LPDDR4 module */ + 9 14 12 13 10 11 8 15 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 20 22 23 16 19 17 18 21 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 28 24 26 27 29 30 31 25 + + /* LP4_PHYS_CH1A */ + + /* DQA[0:7] pins of LPDDR4 module */ + 2 1 6 7 5 4 3 0 + /* DQA[8:15] pins of LPDDR4 module */ + 11 10 8 9 12 15 13 14 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 17 23 19 16 21 22 20 18 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 31 29 26 25 28 27 24 30 + + /* LP4_PHYS_CH1B */ + + /* DQA[0:7] pins of LPDDR4 module */ + 4 3 7 5 6 1 0 2 + /* DQA[8:15] pins of LPDDR4 module */ + 15 9 8 11 14 13 12 10 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 20 23 22 21 18 19 16 17 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 25 28 30 31 26 27 24 29>; +}; diff --git a/board/google/Kconfig b/board/google/Kconfig index 679a0f10239..1d67fda0676 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -60,8 +60,23 @@ config TARGET_CHROMEBOOK_SAMUS_TPL between different A/B versions of SPL/U-Boot, to allow upgrading of almost all U-Boot code in the field. +config TARGET_CHROMEBOOK_CORAL + bool "Chromebook coral" + help + This is a range of Intel-based laptops released in 2018. They use an + Intel Apollolake CPU. The design supports WiFi, 4GB to 16GB of + LPDDR4 1600MHz SDRAM, PCIe WiFi and Bluetooth, eMMC (typically 32GB), + up two cameras (front-facing 720p and another 5MP option), USB SD + reader, microphone and speakers. It also includes two USB 3 Type A and + two Type C ports. The latter are used as power input and can also + charge external devices as well as a 4K external display. There is a + Chrome OS EC connected on LPC, a Cr50 secure chip from Google and + various display options. OEMs products include Acer Chromebook 11 + (e.g. C732, CB11, CP311) and Lenovo Chromebook (100e, 300e, 500e). + endchoice +source "board/google/chromebook_coral/Kconfig" source "board/google/chromebook_link/Kconfig" source "board/google/chromebox_panther/Kconfig" source "board/google/chromebook_samus/Kconfig" diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig new file mode 100644 index 00000000000..940bee89b0b --- /dev/null +++ b/board/google/chromebook_coral/Kconfig @@ -0,0 +1,43 @@ +if TARGET_CHROMEBOOK_CORAL + +config SYS_BOARD + default "chromebook_coral" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "apollolake" + +config SYS_CONFIG_NAME + default "chromebook_coral" + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + +config PCIE_ECAM_BASE + default 0xf0000000 + +config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + help + Allow post codes to be sent to the Chroem OS EC early during boot, + to enable monitoring of the boot and debugging when things go wrong. + With this option enabled, the EC console can be used to watch post + codes the first part of boot. + +config SYS_CAR_ADDR + hex + default 0xfef00000 + +config SYS_CAR_SIZE + hex + default 0xc0000 + +endif diff --git a/board/google/chromebook_coral/MAINTAINERS b/board/google/chromebook_coral/MAINTAINERS new file mode 100644 index 00000000000..904227e2e21 --- /dev/null +++ b/board/google/chromebook_coral/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK_CORAL_BOARD +M: Simon Glass +S: Maintained +F: board/google/chromebook_coral/ +F: include/configs/chromebook_coral.h +F: configs/chromebook_coral_defconfig diff --git a/board/google/chromebook_coral/Makefile b/board/google/chromebook_coral/Makefile new file mode 100644 index 00000000000..6a27ce3da1b --- /dev/null +++ b/board/google/chromebook_coral/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += coral.o diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c new file mode 100644 index 00000000000..dfe0fa484a1 --- /dev/null +++ b/board/google/chromebook_coral/coral.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + */ + +#include + +int arch_misc_init(void) +{ + return 0; +} + +int board_run_command(const char *cmdline) +{ + printf("No command line\n"); + + return 0; +} diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig new file mode 100644 index 00000000000..6636f7c44ea --- /dev/null +++ b/configs/chromebook_coral_defconfig @@ -0,0 +1,95 @@ +CONFIG_X86=y +CONFIG_SYS_TEXT_BASE=0x1110000 +CONFIG_SYS_MALLOC_F_LEN=0x1d00 +CONFIG_SPL_SYS_MALLOC_F_LEN=0xd000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xde000000 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_VENDOR_GOOGLE=y +CONFIG_TARGET_CHROMEBOOK_CORAL=y +CONFIG_DEBUG_UART=y +CONFIG_FSP_VERSION2=y +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_INTEL_CAR_CQOS=y +CONFIG_X86_OFFSET_U_BOOT=0xffe00000 +CONFIG_X86_OFFSET_SPL=0xffe80000 +CONFIG_SPL_TEXT_BASE=0xfef10000 +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_LOG=y +CONFIG_LOG_DEFAULT_LEVEL=7 +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_BLOBLIST=y +# CONFIG_TPL_BLOBLIST is not set +CONFIG_BLOBLIST_ADDR=0x100000 +CONFIG_HANDOFF=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_CPU_SUPPORT=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_PCI=y +# CONFIG_TPL_SPI_SUPPORT is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_PMC=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_PART=y +CONFIG_CMD_SATA=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_TPM=y +CONFIG_CMD_TPM_TEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +# CONFIG_SPL_MAC_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="chromebook_coral" +# CONFIG_NET is not set +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CPU=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_TPL_MISC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y +# CONFIG_SPI_FLASH is not set +CONFIG_SPI_FLASH_INTEL_FAST=y +# CONFIG_X86_PCH7 is not set +# CONFIG_X86_PCH9 is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SOUND=y +CONFIG_SOUND_I8254=y +CONFIG_SOUND_RT5677=y +CONFIG_SPI=y +CONFIG_TPL_SYSRESET=y +CONFIG_TPM_TIS_LPC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +# CONFIG_DM_VIDEO is not set +CONFIG_SPL_FS_CBFS=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_TPL_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_TPM=y +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst new file mode 100644 index 00000000000..bf384b5e942 --- /dev/null +++ b/doc/board/google/chromebook_coral.rst @@ -0,0 +1,25 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Simon Glass + +Chromebook Coral +================ + +Here are some random notes, to be expanded. + +Hob size returned from FSP is about 53KB. + +Partial ROM map + +fef07000 TPL/SPL Stack top +fef10000 +fef16000 2a000 FSP M default stack +fef40000 SPL +fef71000 59000 FSP M +fefca000 + +Partial memory map + +CONFIG_BLOBLIST_ADDR=0x100000 + + +[1] Intel PDF https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h new file mode 100644 index 00000000000..5e447362ada --- /dev/null +++ b/include/configs/chromebook_coral.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + */ + +/* + * board/config.h - configuration options, board-specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +#undef CONFIG_STD_DEVICES_SETTINGS +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ + "stdout=vidconsole,serial\0" \ + "stderr=vidconsole,serial\0" + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x003f8000 + +#define CONFIG_TPL_TEXT_BASE 0xffff8000 + +#define CONFIG_SYS_NS16550_MEM32 +#undef CONFIG_SYS_NS16550_PORT_MAPPED + +#endif /* __CONFIG_H */