From patchwork Wed Sep 25 15:00:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1167517 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Wfy6uwWU"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46dkYP12B1z9sNx for ; Thu, 26 Sep 2019 02:49:29 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id CA181C2218E; Wed, 25 Sep 2019 16:49:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 47892C22030; Wed, 25 Sep 2019 15:07:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D1F31C22180; Wed, 25 Sep 2019 15:07:43 +0000 (UTC) Received: from mail-io1-f66.google.com (mail-io1-f66.google.com [209.85.166.66]) by lists.denx.de (Postfix) with ESMTPS id 59117C22161 for ; Wed, 25 Sep 2019 15:02:36 +0000 (UTC) Received: by mail-io1-f66.google.com with SMTP id z19so14709289ior.0 for ; Wed, 25 Sep 2019 08:02:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rCFCOHbgKOZ61z1fkQsU9ZyWv/OkbNaprCKiLt6YRkg=; b=Wfy6uwWUiZzCHn0V8eilDkyEiwRGvShlMuJAOWnqtoZK0fzYjf/SpaCBq6tbTY9TNY llD+2C20ZHSurv1CbRRvbO/aLeUAqkwlRRrHuQBd3kvjiDEBMYhcqaEiYnKMr8cnXsFt v8cZzcFX6HRPcOVyWy4EDnxgSPPl2erEJgbZE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rCFCOHbgKOZ61z1fkQsU9ZyWv/OkbNaprCKiLt6YRkg=; b=M79nx+vOSiSN3lLtsSGF+b3gxkOrVZtUOJlr4U+haal5lzFS9tikV0qwsCNftbfBxO vBoQNMmyFgARPOqYIuqMlCjMYiY26Oi7eaV71N6UVaXjmwJCUR1UqfSyCdmpmK6f9aD9 Ztgsa0mIZIkCLlfZL4z5bWG7FH3S8xpZhvTjTDAvwO94/KSGxIsrVAhFLb2SWC7fBu5+ zbFw5fmJ/zdYqaKE5s00qTFPgNhkgn0X1nAzqw2igyVRSgLm/rlrhWPcP2M/9YmImC6N 8OuonPONvXJWOFbvp9a5wVG2gsUyEsqbP2d3N60t8/vvon6xpuAOzA38xwPLVFLbfTms gviQ== X-Gm-Message-State: APjAAAXHSA0ox0HjDAL9EYREiezmQPaFBQxEiv5aOKlJpWoYeOryRz/y KXU7aGfZVokPlovc3fG4LW7jzCKrpz4= X-Google-Smtp-Source: APXvYqzq9IhmIrKIj/z632eKs3DNsx9Fl0mjZNw9upJpq0lgR12DedGsWMuea3B1JN3gD8q6bpymaA== X-Received: by 2002:a92:dc89:: with SMTP id c9mr806163iln.215.1569423754945; Wed, 25 Sep 2019 08:02:34 -0700 (PDT) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id 197sm6758613ioc.78.2019.09.25.08.02.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 08:02:34 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Wed, 25 Sep 2019 09:00:40 -0600 Message-Id: <20190925150052.201698-115-sjg@chromium.org> X-Mailer: git-send-email 2.23.0.444.g18eeb5a265-goog In-Reply-To: <20190925150052.201698-102-sjg@chromium.org> References: <20190925150052.201698-102-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH 114/126] x86: apollolake: Add hostbridge driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This driver models the hostbridge as a northbridge. It simply sets up the graphics BAR. It supports of-platdata. Signed-off-by: Simon Glass --- arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/hostbridge.c | 127 +++++++++++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 arch/x86/cpu/apollolake/hostbridge.c diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 5d5fc0b5949..13113fadc79 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -5,5 +5,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o obj-y += gpio.o +obj-y += hostbridge.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c new file mode 100644 index 00000000000..5b3cd6d292a --- /dev/null +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include + +/** + * struct apl_hostbridge_platdata - platform data for hostbridge + * + * @pciex_region_size: BAR length in bytes + * @bdf: Bus/device/function of hostbridge + */ +struct apl_hostbridge_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_hostbridge dtplat; +#endif + uint pciex_region_size; + pci_dev_t bdf; +}; + +enum { + PCIEXBAR = 0x60, + PCIEXBAR_LENGTH_256MB = 0, + PCIEXBAR_LENGTH_128MB, + PCIEXBAR_LENGTH_64MB, + + PCIEXBAR_PCIEXBAREN = 1 << 0, + + TSEG = 0xb8, /* TSEG base */ +}; + +static int apl_hostbridge_early_init(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + u32 region_size; + u32 reg; + ulong base; + + /* Set up the MCHBAR */ + pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32); + base = MCH_BASE_ADDRESS; + pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32); + + /* + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB + */ + pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32); + + switch (plat->pciex_region_size >> 20) { + default: + case 256: + region_size = PCIEXBAR_LENGTH_256MB; + break; + case 128: + region_size = PCIEXBAR_LENGTH_128MB; + break; + case 64: + region_size = PCIEXBAR_LENGTH_64MB; + break; + } + + reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1) + | PCIEXBAR_PCIEXBAREN; + pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32); + + /* + * TSEG defines the base of SMM range. BIOS determines the base + * of TSEG memory which must be at or below Graphics base of GTT + * Stolen memory, hence its better to clear TSEG register early + * to avoid power on default non-zero value (if any). + */ + pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32); + + return 0; +} + +static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + int root; + + /* Get length of PCI Express Region */ + plat->pciex_region_size = dev_read_u32_default(dev, "pciex-region-size", + 256 << 20); + + root = pci_x86_get_devfn(dev); + if (root < 0) + return log_msg_ret("Cannot get host-bridge PCI address", root); + plat->bdf = root; +#else + plat->pciex_region_size = plat->dtplat.pciex_region_size; + plat->bdf = pci_x86_ofplat_get_devfn(plat->dtplat.reg[0]); +#endif + + return 0; +} + +static int apl_hostbridge_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_TPL) + return apl_hostbridge_early_init(dev); + + return 0; +} + +static const struct udevice_id apl_hostbridge_ids[] = { + { .compatible = "intel,apl-hostbridge" }, + { } +}; + +U_BOOT_DRIVER(apl_hostbridge_drv) = { + .name = "intel_apl_hostbridge", + .id = UCLASS_NORTHBRIDGE, + .of_match = apl_hostbridge_ids, + .ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata, + .probe = apl_hostbridge_probe, + .platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata), +};