From patchwork Wed Sep 25 15:00:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1167478 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="UhNJWvT2"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46djxf6wLQz9sNx for ; Thu, 26 Sep 2019 02:21:58 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A1B0AC22156; Wed, 25 Sep 2019 16:16:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6009DC21F90; Wed, 25 Sep 2019 15:07:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2923EC21F90; Wed, 25 Sep 2019 15:07:00 +0000 (UTC) Received: from mail-io1-f68.google.com (mail-io1-f68.google.com [209.85.166.68]) by lists.denx.de (Postfix) with ESMTPS id 25728C2215B for ; Wed, 25 Sep 2019 15:02:19 +0000 (UTC) Received: by mail-io1-f68.google.com with SMTP id a1so14678833ioc.6 for ; Wed, 25 Sep 2019 08:02:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u9/AWttthcuT1CSiXw9jtJ98LWKzE59bNibXSYZrHG0=; b=UhNJWvT2TftD5SjBnzZGlxNX5afc45/i8McgK5/YUaeSTW8d81Tq3J+Hdqyuc/VZD1 roJ3RxTLz7gDdvk+Jce2d4uQuSo9Gmm4mxaoJnlBCRqiOMzGA973aPHvrTSH8mLTjkp/ /4h+6kxnSizd9jmRWDyKzUX97xq2oRznmiB6c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u9/AWttthcuT1CSiXw9jtJ98LWKzE59bNibXSYZrHG0=; b=M07/keDGlyTwIC2iDyMJvXDKGV0Z/uQ3MltXIynQbJG1faszz7LbWwX5l94fUFPieP r0BAnAkWvfJqCuSS9WGPBvsdmjCmg77pYqUv5cCg7qAL6AanaeMAwFq+SlxLlEfRz2un ZECjwMs4DYWcjWpRlOP+1MAe8rFNPCmuci4DveDbl3lMJoWRmVmBllzIYM4UZKajPEtp AoqUQToEXH2onnaDrBns/vZDYpU+emG9vshNfKBTUQq8XrF9LVg25Zf/Lq/k4rCA7+Gj YrxPDfyRdFbbVz6ArjGXV6gcV9oy0vSl6Af9n6aibfTU8slu3t2ewNSgAxMxJvwnXlp1 38/Q== X-Gm-Message-State: APjAAAXifTknU+9GegfWoWRAJTogg1aWq3ALZnGHTuqfmxcWE3nchiiX Lu4Wq5KxfMGbyYWVXU2e6i6NCY9ikVw= X-Google-Smtp-Source: APXvYqzXhw/qv3d7kZ+W0QrEVJS44GnOHjusy4ReGeoGZ6a269ka/HYLaledd3eKMZS/T/rGrIPPNw== X-Received: by 2002:a5d:8a0f:: with SMTP id w15mr9027384iod.239.1569423737359; Wed, 25 Sep 2019 08:02:17 -0700 (PDT) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id 197sm6758613ioc.78.2019.09.25.08.02.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 08:02:17 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Wed, 25 Sep 2019 09:00:29 -0600 Message-Id: <20190925150052.201698-104-sjg@chromium.org> X-Mailer: git-send-email 2.23.0.444.g18eeb5a265-goog In-Reply-To: <20190925150052.201698-102-sjg@chromium.org> References: <20190925150052.201698-102-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH 103/126] x86: Add an option to control the position of U-Boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The existing work-around for positioning U-Boot in the ROM when it actually runs from RAM still exists and there is not obvious way to change this. Add a proper Kconfig option to handle this case. This also adds a new bool property to indicate whether CONFIG_SYS_TEXT_BASE exists. Signed-off-by: Simon Glass --- Kconfig | 9 ++++++--- arch/x86/Kconfig | 5 +++++ arch/x86/dts/u-boot.dtsi | 18 +++--------------- configs/chromebook_samus_tpl_defconfig | 1 + 4 files changed, 15 insertions(+), 18 deletions(-) diff --git a/Kconfig b/Kconfig index 1f0904f7045..f772d4fbe9f 100644 --- a/Kconfig +++ b/Kconfig @@ -529,9 +529,14 @@ config SYS_EXTRA_OPTIONS configuration to Kconfig. Since this option will be removed sometime, new boards should not use this option. -config SYS_TEXT_BASE +config HAS_SYS_TEXT_BASE + bool depends on !NIOS2 && !XTENSA depends on !EFI_APP + default y + +config SYS_TEXT_BASE + depends on HAS_SYS_TEXT_BASE default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3 default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I @@ -540,8 +545,6 @@ config SYS_TEXT_BASE help The address in memory that U-Boot will be running from, initially. - - config SYS_CLK_FREQ depends on ARC || ARCH_SUNXI || MPC83xx int "CPU clock frequency" diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fce3c1d92a3..02c116caeb7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -891,4 +891,9 @@ config CACHE_QOS_SIZE_PER_BIT depends on INTEL_CAR_CQOS default 0x20000 # 128 KB +config X86_OFFSET_U_BOOT + hex "Offset of U-Boot in ROM image" + depends on HAS_SYS_TEXT_BASE + default SYS_TEXT_BASE + endmenu diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 189be2196cb..f33f276b90d 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -54,7 +54,7 @@ u-boot-spl-dtb { }; u-boot { - offset = ; + offset = ; }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { @@ -64,23 +64,11 @@ type = "u-boot-dtb-with-ucode"; }; u-boot { - /* - * TODO(sjg@chromium.org): - * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But - * for boards with textbase in SDRAM we cannot do this. Just use - * an assumed-valid value (1MB before the end of flash) here so - * that we can actually build an image for coreboot, etc. - * We need a better solution, perhaps a separate Kconfig. - */ -#if CONFIG_SYS_TEXT_BASE == 0x1110000 - offset = <0xfff00000>; -#else - offset = ; -#endif + offset = ; }; #else u-boot-with-ucode-ptr { - offset = ; + offset = ; }; #endif #ifdef CONFIG_HAVE_MICROCODE diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 28f23cfe125..c7f125eaa40 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -13,6 +13,7 @@ CONFIG_HAVE_REFCODE=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_SPL_TEXT_BASE=0xffe70000 +CONFIG_X86_OFFSET_U_BOOT=0xfff00000 CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_SHOW_BOOT_PROGRESS=y