From patchwork Wed Aug 28 10:46:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1154342 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46JN2j0g4lz9sBp for ; Wed, 28 Aug 2019 20:56:12 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B0148C21EC2; Wed, 28 Aug 2019 10:53:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2D9E8C21E13; Wed, 28 Aug 2019 10:53:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 88EC1C21F0C; Wed, 28 Aug 2019 10:53:02 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id D3AC5C21E73 for ; Wed, 28 Aug 2019 10:53:01 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x7SAe62H081020; Wed, 28 Aug 2019 18:40:06 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Wed, 28 Aug 2019 18:52:39 +0800 From: Andes To: Date: Wed, 28 Aug 2019 18:46:07 +0800 Message-ID: <20190828104611.3315-5-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190828104611.3315-1-uboot@andestech.com> References: <20190828104611.3315-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x7SAe62H081020 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v4 4/8] riscv: ae350: use the v5l2 driver to configure the cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Find the UCLASS_CACHE driver to configure the cache controller's settings. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- board/AndesTech/ax25-ae350/ax25-ae350.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 3d65ce7..b43eebb 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -93,10 +94,18 @@ int smc_init(void) return 0; } +static void v5l2_init(void) +{ + struct udevice *dev; + + uclass_get_device(UCLASS_CACHE, 0, &dev); +} + #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { smc_init(); + v5l2_init(); return 0; }