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Tue, 27 Aug 2019 06:25:14 +0000 Received: from AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::5d98:e1f4:aa72:16b4]) by AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::5d98:e1f4:aa72:16b4%4]) with mapi id 15.20.2178.022; Tue, 27 Aug 2019 06:25:14 +0000 From: Peng Fan To: "sbabic@denx.de" , "festevam@gmail.com" , "lukma@denx.de" Thread-Topic: [PATCH V3 11/27] imx8m: update imx-regs for i.MX8MM Thread-Index: AQHVXKAv9KkvjF96cE6xdDcC0Oke+g== Date: Tue, 27 Aug 2019 06:25:14 +0000 Message-ID: <20190827064033.28973-12-peng.fan@nxp.com> References: <20190827064033.28973-1-peng.fan@nxp.com> In-Reply-To: <20190827064033.28973-1-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.16.4 x-clientproxiedby: HK2PR03CA0066.apcprd03.prod.outlook.com (2603:1096:202:17::36) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.71] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8655d62d-0e44-4b2a-a4d3-08d72ab751f8 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB6675; H:AM0PR04MB4481.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: XANq5wG1a6fymhbLNZLQV/G09WEHAoL/zMvLrNWvsmQw79LwjCuZ56jOO0ZDLANuFRNKchTvgKRUaTeJM4YyPbVRK0tfSpcnHfzLzZO1Ll2hwiCoepz8ZhkPQocuDRaqnFvWMoQMlRExez2R3ngNPcgkS4Gso34Z+/28EwL14ZWQJQui+QLzaEPmxH6KCUDLOckh7YSFPeykyNI5yPtY4dZPrgFbwtl6yS1aahTSeQcC47olXcCBIG9loiSN/TC0LM7wrEqK6pJgkQYNhkqgd5+xXTBN/te4il8CEzzyCeqDaKdg2G5PV2M0bVqq6hsNvgcRt15LjlhoseI73cJoVRNovWVA/zg981ZXGpLDvG0TArI+DyRkA4FqZvX2ryFUfPfZidoyIPVdvKLgjXal/ULlqwmFT9Rfe/ID6TR83eI= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8655d62d-0e44-4b2a-a4d3-08d72ab751f8 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Aug 2019 06:25:14.0874 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hI/KF4wIfcofpYbo8vQe3Gu8OqIjEMwd3fR66DRHDHn/ey1DZwb/O5vgmQUpWs+cjSWfDJRmGDDdHQCo/3r1OA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6675 Cc: "u-boot@lists.denx.de" , dl-uboot-imx Subject: [U-Boot] [PATCH V3 11/27] imx8m: update imx-regs for i.MX8MM X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" i.MX8MM has similar architecture with i.MX8MQ, but it has totally different PLL design and register layout change. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 69 +++++++++++++++++++++++++++--- 1 file changed, 64 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 4ce6c1b077..62640d996e 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -10,8 +10,8 @@ #include -#define ROM_VERSION_A0 0x800 -#define ROM_VERSION_B0 0x83C +#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800 +#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800 #define M4_BOOTROM_BASE_ADDR 0x007E0000 @@ -23,7 +23,6 @@ #define WDOG1_BASE_ADDR 0x30280000 #define WDOG2_BASE_ADDR 0x30290000 #define WDOG3_BASE_ADDR 0x302A0000 -#define LCDIF_BASE_ADDR 0x30320000 #define IOMUXC_BASE_ADDR 0x30330000 #define IOMUXC_GPR_BASE_ADDR 0x30340000 #define OCOTP_BASE_ADDR 0x30350000 @@ -46,10 +45,14 @@ #define UART4_BASE_ADDR 0x30A60000 #define USDHC1_BASE_ADDR 0x30B40000 #define USDHC2_BASE_ADDR 0x30B50000 +#ifdef CONFIG_IMX8MM +#define USDHC3_BASE_ADDR 0x30B60000 +#endif #define TZASC_BASE_ADDR 0x32F80000 -#define MXS_LCDIF_BASE LCDIF_BASE_ADDR +#define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \ + 0x30320000 : 0x32e00000 #define SRC_IPS_BASE_ADDR 0x30390000 #define SRC_DDRC_RCR_ADDR 0x30391000 @@ -134,6 +137,7 @@ struct fuse_bank1_regs { u32 rsvd3[3]; }; +#ifdef CONFIG_IMX8MQ struct anamix_pll { u32 audio_pll1_cfg0; u32 audio_pll1_cfg1; @@ -168,6 +172,60 @@ struct anamix_pll { u32 frac_pllout_div_cfg; u32 sscg_pllout_div_cfg; }; +#else +struct anamix_pll { + u32 audio_pll1_gnrl_ctl; + u32 audio_pll1_fdiv_ctl0; + u32 audio_pll1_fdiv_ctl1; + u32 audio_pll1_sscg_ctl; + u32 audio_pll1_mnit_ctl; + u32 audio_pll2_gnrl_ctl; + u32 audio_pll2_fdiv_ctl0; + u32 audio_pll2_fdiv_ctl1; + u32 audio_pll2_sscg_ctl; + u32 audio_pll2_mnit_ctl; + u32 video_pll1_gnrl_ctl; + u32 video_pll1_fdiv_ctl0; + u32 video_pll1_fdiv_ctl1; + u32 video_pll1_sscg_ctl; + u32 video_pll1_mnit_ctl; + u32 reserved[5]; + u32 dram_pll_gnrl_ctl; + u32 dram_pll_fdiv_ctl0; + u32 dram_pll_fdiv_ctl1; + u32 dram_pll_sscg_ctl; + u32 dram_pll_mnit_ctl; + u32 gpu_pll_gnrl_ctl; + u32 gpu_pll_div_ctl; + u32 gpu_pll_locked_ctl1; + u32 gpu_pll_mnit_ctl; + u32 vpu_pll_gnrl_ctl; + u32 vpu_pll_div_ctl; + u32 vpu_pll_locked_ctl1; + u32 vpu_pll_mnit_ctl; + u32 arm_pll_gnrl_ctl; + u32 arm_pll_div_ctl; + u32 arm_pll_locked_ctl1; + u32 arm_pll_mnit_ctl; + u32 sys_pll1_gnrl_ctl; + u32 sys_pll1_div_ctl; + u32 sys_pll1_locked_ctl1; + u32 reserved2[24]; + u32 sys_pll1_mnit_ctl; + u32 sys_pll2_gnrl_ctl; + u32 sys_pll2_div_ctl; + u32 sys_pll2_locked_ctl1; + u32 sys_pll2_mnit_ctl; + u32 sys_pll3_gnrl_ctl; + u32 sys_pll3_div_ctl; + u32 sys_pll3_locked_ctl1; + u32 sys_pll3_mnit_ctl; + u32 anamix_misc_ctl; + u32 anamix_clk_mnit_ctl; + u32 reserved3[437]; + u32 digprog; +}; +#endif struct fuse_bank9_regs { u32 mac_addr0; @@ -239,7 +297,8 @@ struct bootrom_sw_info { u32 reserved_3[3]; }; -#define ROM_SW_INFO_ADDR_B0 0x00000968 +#define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\ + 0x000009e8) #define ROM_SW_INFO_ADDR_A0 0x000009e8 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \