From patchwork Tue Aug 20 09:35:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1149979 X-Patchwork-Delegate: prabhakar@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46CQyr44h4z9sN4 for ; Tue, 20 Aug 2019 19:50:44 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2B10CC21F6A; Tue, 20 Aug 2019 09:48:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3C651C21F87; Tue, 20 Aug 2019 09:46:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 21C27C21F68; Tue, 20 Aug 2019 09:46:03 +0000 (UTC) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lists.denx.de (Postfix) with ESMTPS id 1B733C21F9B for ; Tue, 20 Aug 2019 09:46:01 +0000 (UTC) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E2F601A005B; Tue, 20 Aug 2019 11:46:00 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6849C1A01BE; Tue, 20 Aug 2019 11:45:54 +0200 (CEST) Received: from titan.ap.freescale.net (TITAN.ap.freescale.net [10.192.208.233]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 10E0C40318; Tue, 20 Aug 2019 17:45:43 +0800 (SGT) From: Hou Zhiqiang To: u-boot@lists.denx.de, prabhakar.kushwaha@nxp.com, wd@denx.de, Shengzhou.Liu@nxp.com, priyanka.jain@nxp.com, sjg@chromium.org, marek.vasut+renesas@gmail.com, sr@denx.de, jagdish.gediya@nxp.com, bmeng.cn@gmail.com, york.sun@nxp.com, Jiafei.Pan@nxp.com, Xiaowei.Bao@nxp.com Date: Tue, 20 Aug 2019 09:35:33 +0000 Message-Id: <20190820093536.39407-12-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190820093536.39407-1-Zhiqiang.Hou@nxp.com> References: <20190820093536.39407-1-Zhiqiang.Hou@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Cc: Hou Zhiqiang Subject: [U-Boot] [PATCHv2 11/14] powerpc: Enable device tree support for P5040DS X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add device tree for P5040DS board and enable CONFIG_OF_CONTROL so that device tree can be compiled. Signed-off-by: Hou Zhiqiang --- V2: - No change. arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/p5040.dtsi | 62 ++++++++++++++++++++++++++++++++++++++ arch/powerpc/dts/p5040ds.dts | 18 +++++++++++ configs/P5040DS_NAND_defconfig | 3 ++ configs/P5040DS_SDCARD_defconfig | 3 ++ configs/P5040DS_SPIFLASH_defconfig | 3 ++ configs/P5040DS_defconfig | 3 ++ 7 files changed, 93 insertions(+) create mode 100644 arch/powerpc/dts/p5040.dtsi create mode 100644 arch/powerpc/dts/p5040ds.dts diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index ffd929c..0e234cc 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb +dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi new file mode 100644 index 0000000..b6f6c5d --- /dev/null +++ b/arch/powerpc/dts/p5040.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P5040 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e5500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e5500@0 { + device_type = "cpu"; + reg = <0>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e5500@1 { + device_type = "cpu"; + reg = <1>; + fsl,portid-mapping = <0x40000000>; + }; + cpu2: PowerPC,e5500@2 { + device_type = "cpu"; + reg = <2>; + fsl,portid-mapping = <0x20000000>; + }; + cpu3: PowerPC,e5500@3 { + device_type = "cpu"; + reg = <3>; + fsl,portid-mapping = <0x10000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; +}; diff --git a/arch/powerpc/dts/p5040ds.dts b/arch/powerpc/dts/p5040ds.dts new file mode 100644 index 0000000..723d31d --- /dev/null +++ b/arch/powerpc/dts/p5040ds.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P5040DS Device Tree Source + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p5040.dtsi" + +/ { + model = "fsl,P5040DS"; + compatible = "fsl,P5040DS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + +}; diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index b2c61d7..cbccb4c 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P5040DS=y +CONFIG_DEFAULT_DEVICE_TREE="p5040ds" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index dbff8f7..cdefb2d 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P5040DS=y +CONFIG_DEFAULT_DEVICE_TREE="p5040ds" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 1552f84..c636b16 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P5040DS=y +CONFIG_DEFAULT_DEVICE_TREE="p5040ds" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index e8ff36e..6572ff1 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P5040DS=y +CONFIG_DEFAULT_DEVICE_TREE="p5040ds" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y