diff mbox series

[U-Boot,v3,3/6] net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071

Message ID 20190729190014.29526-4-agust@denx.de
State Superseded
Delegated to: Joe Hershberger
Headers show
Series Extend mv88e61xx driver to support 88E6071 | expand

Commit Message

Anatolij Gustschin July 29, 2019, 7 p.m. UTC 
On mv88E6071 the 'EDet' field offset, width and sense control
bits are different, adjust the driver to init the PHY control
register as needed. This fixes not working link detection and
tftp transfers.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
---
 drivers/net/phy/mv88e61xx.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

Comments

Joe Hershberger July 29, 2019, 11:35 p.m. UTC | #1 
On Mon, Jul 29, 2019 at 2:01 PM Anatolij Gustschin <agust@denx.de> wrote:
>
> On mv88E6071 the 'EDet' field offset, width and sense control
> bits are different, adjust the driver to init the PHY control
> register as needed. This fixes not working link detection and
> tftp transfers.
>
> Signed-off-by: Anatolij Gustschin <agust@denx.de>
> Reviewed-by: Chris Packham <judge.packham@gmail.com>
> Tested-by: Chris Packham <judge.packham@gmail.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff mbox series

Patch

diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index feb15d8306..9e9caa63df 100644
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -117,14 +117,12 @@ 
 
 #define SERDES_REG_CTRL_1_FORCE_LINK	BIT(10)
 
-#define PHY_REG_CTRL1_ENERGY_DET_SHIFT	8
-#define PHY_REG_CTRL1_ENERGY_DET_WIDTH	2
-
 /* Field values */
 #define PORT_REG_CTRL_PSTATE_DISABLED	0
 #define PORT_REG_CTRL_PSTATE_FORWARD	3
 
 #define PHY_REG_CTRL1_ENERGY_DET_OFF	0
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE	1
 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY	2
 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT	3
 
@@ -194,6 +192,9 @@  struct mv88e61xx_phy_priv {
 	u8 port_stat_speed_width;/* Width of speed status bitfield */
 	u8 global1;	/* Offset of Switch Global 1 registers */
 	u8 global2;	/* Offset of Switch Global 2 registers */
+	u8 phy_ctrl1_en_det_shift; /* 'EDet' bit field offset */
+	u8 phy_ctrl1_en_det_width; /* Width of 'EDet' bit field */
+	u8 phy_ctrl1_en_det_ctrl;  /* 'EDet' control value */
 };
 
 static inline int smi_cmd(int cmd, int addr, int reg)
@@ -842,6 +843,7 @@  static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
 
 static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
 {
+	struct mv88e61xx_phy_priv *priv = phydev->priv;
 	int val;
 
 	/*
@@ -851,9 +853,9 @@  static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
 	val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
 	if (val < 0)
 		return val;
-	val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
-			       PHY_REG_CTRL1_ENERGY_DET_WIDTH,
-			       PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
+	val = bitfield_replace(val, priv->phy_ctrl1_en_det_shift,
+			       priv->phy_ctrl1_en_det_width,
+			       priv->phy_ctrl1_en_det_ctrl);
 	val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
 	if (val < 0)
 		return val;
@@ -971,12 +973,20 @@  static int mv88e61xx_probe(struct phy_device *phydev)
 		priv->port_stat_link_mask = BIT(11);
 		priv->port_stat_dup_mask = BIT(10);
 		priv->port_stat_speed_width = 2;
+		priv->phy_ctrl1_en_det_shift = 8;
+		priv->phy_ctrl1_en_det_width = 2;
+		priv->phy_ctrl1_en_det_ctrl =
+			PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT;
 		break;
 	case PORT_SWITCH_ID_6071:
 		priv->port_count = 7;
 		priv->port_stat_link_mask = BIT(12);
 		priv->port_stat_dup_mask = BIT(9);
 		priv->port_stat_speed_width = 1;
+		priv->phy_ctrl1_en_det_shift = 14;
+		priv->phy_ctrl1_en_det_width = 1;
+		priv->phy_ctrl1_en_det_ctrl =
+			PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE;
 		break;
 	default:
 		free(priv);