From patchwork Tue Jul 16 16:28:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dalon L Westergreen X-Patchwork-Id: 1132852 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45p5S93q6cz9sN4 for ; Wed, 17 Jul 2019 02:28:39 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 603FAC21E34; Tue, 16 Jul 2019 16:28:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 36DF0C21CB1; Tue, 16 Jul 2019 16:28:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7313DC21CB1; Tue, 16 Jul 2019 16:28:31 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lists.denx.de (Postfix) with ESMTPS id 86D9FC21C6A for ; Tue, 16 Jul 2019 16:28:30 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2019 09:28:28 -0700 X-IronPort-AV: E=Sophos;i="5.63,498,1557212400"; d="scan'208";a="161473299" Received: from dwesterg-mobl.amr.corp.intel.com (HELO dwesterg-mobl1.amr.corp.intel.com) ([10.252.203.146]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2019 09:28:27 -0700 From: Dalon Westergreen To: u-boot@lists.denx.de, marex@denx.de, chin.liang.see@intel.com, dinguyen@kernel.org, tien.fong.chee@intel.com, simon.k.r.goldschmidt@gmail.com, ley.foon.tan@intel.com, rod.frazer@intel.com Date: Tue, 16 Jul 2019 09:28:10 -0700 Message-Id: <20190716162810.14757-1-dalon.westergreen@linux.intel.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Subject: [U-Boot] [PATCH] fpga: arria10: Fix error in fpga pin configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Dalon Westergreen Pin configuration of the FPGA devicetree block should be done after core configuration in the arria10 fpga driver. This fix corrects the check of status, and ensures that the fpga pin mux is configured on correct configuration of the core fpga image. Signed-off-by: Dalon Westergreen --- drivers/fpga/socfpga_arria10.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 285280e507..5fb9d6a191 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -936,10 +936,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) fpgamgr_program_write(rbf_data, rbf_size); status = fpgamgr_program_finish(); - if (status) { - config_pins(gd->fdt_blob, "fpga"); - puts("FPGA: Enter user mode.\n"); - } + if (status) + return status; + + config_pins(gd->fdt_blob, "fpga"); + puts("FPGA: Enter user mode.\n"); return status; }